An SSVEP-actuated brain computer interface using phase-tagged flickering sequences: a cursor system.

This study presents a new steady-state visual evoked potential (SSVEP)-based brain computer interface (BCI). SSVEPs, induced by phase-tagged flashes in eight light emitting diodes (LEDs), were used to control four cursor movements (up, right, down, and left) and four button functions (on, off, right-, and left-clicks) on a screen menu. EEG signals were measured by one EEG electrode placed at Oz position, referring to the international EEG 10-20 system. Since SSVEPs are time-locked and phase-locked to the onsets of SSVEP flashes, EEG signals were bandpass-filtered and segmented into epochs, and then averaged across a number of epochs to sharpen the recorded SSVEPs. Phase lags between the measured SSVEPs and a reference SSVEP were measured, and targets were recognized based on these phase lags. The current design used eight LEDs to flicker at 31.25 Hz with 45 degrees phase margin between any two adjacent SSVEP flickers. The SSVEP responses were filtered within 29.25-33.25 Hz and then averaged over 60 epochs. Owing to the utilization of high-frequency flickers, the induced SSVEPs were away from low-frequency noises, 60 Hz electricity noise, and eye movement artifacts. As a consequence, we achieved a simple architecture that did not require eye movement monitoring or other artifact detection and removal. The high-frequency design also achieved a flicker fusion effect for better visualization. Seven subjects were recruited in this study to sequentially input a command sequence, consisting of a sequence of eight cursor functions, repeated three times. The accuracy and information transfer rate (mean +/- SD) over the seven subjects were 93.14 +/- 5.73% and 28.29 +/- 12.19 bits/min, respectively. The proposed system can provide a reliable channel for severely disabled patients to communicate with external environments.

Implementation of pipelined FastICA on FPGA for real-time blind source separation.

Fast independent component analysis (FastICA) algorithm separates the independent sources from their mixtures by measuring non-Gaussian. FastICA is a common offline method to identify artifact and interference from their mixtures such as electroencephalogram (EEG), magnetoencephalography (MEG), and electrocardiogram (ECG). Therefore, it is valuable to implement FastICA for real-time signal processing. In this paper, the FastICA algorithm is implemented in a field-programmable gate array (FPGA), with the ability of real-time sequential mixed signals processing by the proposed pipelined FastICA architecture. Moreover, in order to increase the numbers precision, the hardware floating-point (FP) arithmetic units had been carried out in the hardware FastICA. In addition, the proposed pipeline FastICA provides the high sampling rate (192 kHz) capability by hand coding the hardware FastICA in hardware description language (HDL). To verify the features of the proposed hardware FastICA, simulations are first performed, then real-time signal processing experimental results are presented using the fabricated platform. Experimental results demonstrate the effectiveness of the presented hardware FastICA as expected.