Effects of the F4TCNQ-Doped Pentacene Interlayers on Performance Improvement of Top-Contact Pentacene-Based Organic Thin-Film Transistors.

In this paper, the top-contact (TC) pentacene-based organic thin-film transistor (OTFT) with a tetrafluorotetracyanoquinodimethane (F4TCNQ)-doped pentacene interlayer between the source/drain electrodes and the pentacene channel layer were fabricated using the co-evaporation method. Compared with a pentacene-based OTFT without an interlayer, OTFTs with an F4TCNQ:pentacene ratio of 1:1 showed considerably improved electrical characteristics. In addition, the dependence of the OTFT performance on the thickness of the F4TCNQ-doped pentacene interlayer is weaker than that on a Teflon interlayer. Therefore, a molecular doping-type F4TCNQ-doped pentacene interlayer is a suitable carrier injection layer that can improve the TC-OTFT performance and facilitate obtaining a stable process window.

Teflon/SiO2 Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process.

This study proposes a two-photomask process for fabricating amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES) layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon) and SiO2 combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO2 deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity.

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme.

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm²/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.