Traumatic terson syndrome with a peculiar mass lesion and tractional retinal detachment: a case report.

BACKGROUND: To report a case with bilateral Terson syndrome presented with a unique mushroom-like mass lesion on the optic disc along with proliferative vitreoretinopathy and tractional retinal detachment. CASE PRESENTATION: A 33-year-old man was injured during a traffic accident and had diffuse brain swelling and intraocular hemorrhage. Poor vision in both eyes was noted after the patient regained consciousness. B-scan ultrasonography showed extensive vitreous opacity with a posterior vitreous detachment and without obvious retinal detachment. Vitrectomy was performed in both eyes five months after the accident. After clearing up the vitreous opacity, a peculiar pigmented mushroom-like mass lesion was noted in the posterior pole and had severe adhesion to the underneath optic disc. Extensive multilayered peripapillary epiretinal membrane was found covering the posterior pole and led to tractional retinal detachment around the macula. The mass was presumed to be an organized vitreous hemorrhage originated from the optic disc. The extensive and adherent epiretinal membrane together with the mass lesion were removed as much as possible and silicon oil was injected for tamponade. However, in the right eye, the retina redetached under silicon oil, whereas in the left eye, his vision improved to 20/100. CONCLUSIONS: Terson syndrome usually has a favorable prognosis but may be complicated by proliferative vitreoretinopathy and tractional retinal detachment. Careful monitoring is warranted and early vitrectomy should be considered in cases suspecting additional pathologies.

Strain-induced structural defects and their effects on the electrochemical performances of silicon core/germanium shell nanowire heterostructures.

We report on strain-induced structural defect formation in core Si nanowires of a Si/Ge core/shell nanowire heterostructure and the influence of the structural defects on the electrochemical performances in lithium-ion battery anodes based on Si/Ge core/shell nanowire heterostructures. The induced structural defects consisting of stacking faults and dislocations in the core Si nanowire were observed for the first time. The generation of stacking faults in the Si/Ge core/shell nanowire heterostructure is observed to prefer settling in either only the Ge shell region or in both the Ge shell and Si core regions and is associated with the increase of the shell volume fraction. The relaxation of the misfit strain in the [112] oriented core/shell nanowire heterostructure leads to subsequent gliding of Shockley partial dislocations, preferentially forming the twins. The observation of crossover of defect formation is of great importance for understanding heteroepitaxy in radial heterostructures at the nanoscale and for building three dimensional heterostructures for the various applications. Furthermore, the effect of the defect formation on the nanomaterial's functionality is investigated using electrochemical performance tests. The Si/Ge core/shell nanowire heterostructures enhance the gravimetric capacity of lithium ion battery anodes under fast charging/discharging rates compared to Si nanowires. However, the induced structural defects hamper lithiation of the Si/Ge core/shell nanowire heterostructure.

Charge transfer in crystalline germanium/monolayer MoS2 heterostructures prepared by chemical vapor deposition.

Heterostructuring provides novel opportunities for exploring emergent phenomena and applications by developing designed properties beyond those of homogeneous materials. Advances in nanoscience enable the preparation of heterostructures formed incommensurate materials. Two-dimensional (2D) materials, such as graphene and transition metal dichalcogenides, are of particular interest due to their distinct physical characteristics. Recently, 2D/2D heterostructures have opened up new research areas. However, other heterostructures such as 2D/three-dimensional (3D) materials have not been thoroughly studied yet although the growth of 3D materials on 2D materials creating 2D/3D heterostructures with exceptional carrier transport properties has been reported. Here we report a novel heterostructure composed of Ge and monolayer MoS2, prepared by chemical vapor deposition. A single crystalline Ge (110) thin film was grown on monolayer MoS2. The electrical characteristics of Ge and MoS2 in the Ge/MoS2 heterostructure were remarkably different from those of isolated Ge and MoS2. The field-effect conductivity type of the monolayer MoS2 is converted from n-type to p-type by growth of the Ge thin film on top of it. Undoped Ge on MoS2 is highly conducting. The observations can be explained by charge transfer in the heterostructure as opposed to chemical doping via the incorporation of impurities, based on our first-principles calculations.

Kinetic manipulation of silicide phase formation in Si nanowire templates.

The phase formation sequence of silicides in two-dimensional (2-D) structures has been well-investigated due to their significance in microelectronics. Applying high-quality silicides as contacts in nanoscale silicon (Si) devices has caught considerable attention recently for their potential in improving and introducing new functions in nanodevices. However, nucleation and diffusion mechanisms are found to be very different in one-dimensional (1-D) nanostructures, and thus the phase manipulation of silicides is yet to be achieved there. In this work, we report kinetic phase modulations to selectively enhance or hinder the growth rates of targeted nickel (Ni) silicides in a Si nanowire (NW) and demonstrate that Ni31Si12, δ-Ni2Si, θ-Ni2Si, NiSi, and NiSi2 can emerge as the first contacting phase at the silicide/Si interface through these modulations. First, the growth rates of silicides are selectively tuned through template structure modifications. It is demonstrated that the growth rate of diffusion limited phases can be enhanced in a porous Si NW due to a short diffusion path, which suppresses the formation of interface limited NiSi2. In addition, we show that a confining thick shell can be applied around the Si NW to hinder the growth of the silicides with large volume expansion during silicidation, including Ni31Si12, δ-Ni2Si, and θ-Ni2Si. Second, a platinum (Pt) interlayer between the Ni source and the Si NW is shown to effectively suppress the formation of the phases with low Pt solubility, including the dominating NiSi2. Lastly, we show that with the combined applications of the above-mentioned approaches, the lowest resistive NiSi phase can form as the first phase in a solid NW with a Pt interlayer to suppress NiSi2 and a thick shell to hinder Ni31Si12, δ-Ni2Si, and θ-Ni2Si simultaneously. The resistivity and maximum current density of NiSi agree reasonably to reported values.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Crystallinity control of ferromagnetic contacts in stressed nanowire templates and the magnetic domain anisotropy.

We report the controlled growth of single-crystalline ferromagnetic contacts through solid state reaction at nanoscale. Single-crystal Mn(5)Si(3) and Fe(5)Ge(3) contacts were grown within stressed Si and Ge nanowire templates, where oxide-shells were used to exert compressive stress on the silicide or germanide. Compared to polycrystalline silicide and germanide structures observed within bare nanowires, the built-in high strain in the oxide-shelled nanostructures alters the nucleation behavior of the ferromagnetic materials, leading to single crystal growth in the transverse/radial direction. Interestingly, the compressive stress is also found to affect the magnetic anisotropy of the ferromagnetic contacts. In-plane and out-of-plane magnetization were observed in Fe(5)Ge(3) for different crystal orientations, showing distinctly preferred domain orientations. These interesting results display the capability to control both the crystallinity and the magnetic anisotropy of ferromagnetic contacts in engineered nanostructures.

High-frequency self-aligned graphene transistors with transferred gate stacks.

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Kinetic competition model and size-dependent phase selection in 1-D nanostructures.

The first phase selection and the phase formation sequence between metal and silicon (Si) couples are indispensably significant to microelectronics. With increasing scaling of device dimension to nano regime, established thermodynamic and kinetic models in bulk and thin film fail to apply in 1-D nanostructures. Herein, we present an unique size-dependent first phase formation sequence in 1-D nanostructures, with Ni-Si as the model system. Interfacial-limited phase which forms the last in thin film, NiSi(2), appears as the dominant first phase at 300-800 °C due to the elimination of continuous grain boundaries in 1-D silicides. On the other hand, θ-Ni(2)Si, the most competitive diffusion-limited phase takes over NiSi(2) and wins out as the first phase in small diameter nanowires at 800 °C. Kinetic parameters extracted from in situ transmission electron microscope studies and a modified kinetic growth competition model quantitatively explain this observation. An estimated critical diameter from the model agrees reasonably well with observations.

Domain wall motion in synthetic Co2Si nanowires.

We report the synthesis of single crystalline Co(2)Si nanowires and the electrical transport studies of single Co(2)Si nanowire devices at low temperature. The butterfly shaped magnetoresistance shows interesting ferromagnetic features, including negative magnetoresistance, hysteretic switch fields, and stepwise drops in magnetoresistance. The nonsmooth stepwise magnetoresistance response is attributed to magnetic domain wall pinning and depinning motion in the Co(2)Si nanowires probably at crystal or morphology defects. The temperature dependence of the domain wall depinning field is observed and described by a model based on thermally assisted domain wall depinning over a single energy barrier.

The growth and applications of silicides for nanoscale devices.

Metal silicides have been used in silicon technology as contacts to achieve high device performance and desired device functions. The growth and applications of silicide materials have recently attracted increasing interest for nanoscale device applications. Nanoscale silicide materials have been demonstrated with various synthetic approaches. Solid state reaction wherein high quality silicides form through diffusion of metal atoms into silicon nano-templates and the subsequent phase transformation caught significant attention for the fabrication of nanoscale Si devices. Very interestingly, studies on the diffusion and phase transformation processes at the nanoscale have indicated possible deviations from the bulk and the thin film system. Here we present a review of fabrication, growth kinetics, electronic properties and device applications of nanoscale silicides formed through solid state reaction.

A systematic study of atmospheric pressure chemical vapor deposition growth of large-area monolayer graphene.

Graphene has attracted considerable interest as a potential material for future electronics. Although mechanical peel is known to produce high quality graphene flakes, practical applications require continuous graphene layers over a large area. The catalyst-assisted chemical vapor deposition (CVD) is a promising synthetic method to deliver wafer-sized graphene. Here we present a systematic study on the nucleation and growth of crystallized graphene domains in an atmospheric pressure chemical vapor deposition (APCVD) process. Parametric studies show that the mean size of the graphene domains increases with increasing growth temperature and CH4 partial pressure, while the density of domains decreases with increasing growth temperature and is independent of the CH4 partial pressure. Our studies show that nucleation of graphene domains on copper substrate is highly dependent on the initial annealing temperature. A two-step synthetic process with higher initial annealing temperature but lower growth temperature is developed to reduce domain density and achieve high quality full-surface coverage of monolayer graphene films. Electrical transport measurements demonstrate that the resulting graphene exhibits a high carrier mobility of up to 3000 cm2 V-1 s-1 at room temperature.

The influence of surface oxide on the growth of metal/semiconductor nanowires.

We report the critical effects of oxide on the growth of nanostructures through silicide formation. Under an in situ ultrahigh vacuum transmission electron microscope, it is observed from the conversion of Si nanowires into the metallic PtSi grains epitaxially through controlled reactions between lithographically defined Pt pads and Si nanowires. With oxide, instead of contact area, single crystal PtSi grains start forming either near the center between two adjacent pads or from the ends of Si nanowires, resulting in the heterostructure formation of Si/PtSi/Si. Without oxide, transformation from Si into PtSi begins at the contact area between them, resulting in the heterostructure formation of PtSi/Si/PtSi. The nanowire heterostructures have an atomically sharp interface with epitaxial relationships of Si(20-2)//PtSi(10-1) and Si[111]//PtSi[111]. Additionally, it has been observed that the existence of oxide significantly affects not only the growth position but also the growth behavior and the growth rate by two orders of magnitude. Molecular dynamics simulations have been performed to support our experimental results and the proposed growth mechanisms. In addition to fundamental science, the significance of the study matters for future processing techniques in nanotechnology and related applications as well.

Unveiling the formation pathway of single crystalline porous silicon nanowires.

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H(2)O(2)) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H(2)O(2)) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and renucleate on the sidewalls of nanowires to initiate new etching pathways to produce a porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 to 30 m(2) g(-1) and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy.

Synthesis and electric properties of dicobalt silicide nanobelts.

Single crystalline Co(2)Si nanobelts were synthesized for the first time. Temperature-dependent electrical transport studies show the Co(2)Si nanobelts exhibit metallic behavior with a large negative magnetoresistance over 10% at low temperature, which may be attributed to alignment of the spins in surface cobalt atoms.

Growth of nickel silicides in Si and Si/SiOx core/shell nanowires.

We exploited the oxide shell structure to explore the structure confinement effect on the nickel silicide growth in one-dimensional nanowire template. The oxide confinement structure is similar to the contact structure (via hole) in the thin film system or nanodevices passivated by oxide or nitride film. Silicon nanowires in direct contact with nickel pads transform into two phases of nickel silicides, Ni31Si12 and NiSi2, after one-step annealing at 550 °C. In a bare Si nanowire during the annealing process, NiSi2 grows initially through the nanowire, followed by the transformation of NiSi2 into the nickel-rich phase, Ni31Si12 starting from near the nickel pad. Ni31Si12 is also observed under the nickel pads. Although the same phase transformations of Si to nickel silicides are observed in nanowires with oxide confinement structure, the growth rate of nickel silicides, Ni31Si12 and NiSi2, is retarded dramatically. With increasing oxide thickness from 5 to 50 nm, the retarding effect of the Ni31Si12 growth and the annihilation of Ni2Si into the oxide confined-Si is clearly observed. Ni31Si12 and Ni2Si phases are limited to grow into the Si/SiOx core-shell nanowire as the shell thickness reaches 50 nm. It is experimental evidence that phase transformation is influenced by the stressed structure at nanoscale.

Sub-100 nm channel length graphene transistors.

Here we report high-performance sub-100 nm channel length graphene transistors fabricated using a self-aligned approach. The graphene transistors are fabricated using a highly doped GaN nanowire as the local gate with the source and drain electrodes defined through a self-aligned process and the channel length defined by the nanowire size. This fabrication approach allows the preservation of the high carrier mobility in graphene and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords transistor performance not previously possible. Graphene transistors with 45-100 nm channel lengths have been fabricated with the scaled transconductance exceeding 2 mS/µm, comparable to the best performed high electron mobility transistors with similar channel lengths. Analysis of and the device characteristics gives a transit time of 120-220 fs and the projected intrinsic cutoff frequency (f(T)) reaching 700-1400 GHz. This study demonstrates the exciting potential of graphene based electronics in terahertz electronics.

High-speed graphene transistors with a self-aligned nanowire gate.

Graphene has attracted considerable interest as a potential new electronic material. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co(2)Si-Al(2)O(3) core-shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA µm(-1)) and transconductance (1.27 mS µm(-1)) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of f(T) = 100-300 GHz, with the extrinsic f(T) (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic f(T) of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths.

Detection of spin polarized carrier in silicon nanowire with single crystal MnSi as magnetic contacts.

We report the formation of single crystal MnSi nanowires, MnSi/Si/MnSi nanowire heterostructures, to study the spin transport in silicon nanostructure. Scanning electron microscopy studies show that silicon nanowires can be converted into single crystal MnSi nanowires through controlled solid-state reaction. High-resolution transmission electron microscope studies show that MnSi/Si/MnSi heterostructures have clean, atomically sharp interfaces with an epitaxial relationship of Si[311]//MnSi[120] and Si(345)//MnSi(214). Magnetoresistance (MR) studies show that the single crystal MnSi nanowire exhibits metallic behavior with paramagnetic to ferromagnetic transition temperature of 29.7 K and a negative MR up to 1.8% at low temperature. Furthermore, using single crystal MnSi/p-Si/MnSi nanowire heterostructures, we have studied carrier tunneling via the Schottky barrier and spin polarized carrier transport in the silicon nanodevices.

Top-gated graphene nanoribbon transistors with ultrathin high-k dielectrics.

The integration ultrathin high dielectric constant (high-k) materials with graphene nanoribbons (GNRs) for top-gated transistors can push their performance limit for nanoscale electronics. Here we report the assembly of Si/HfO(2) core/shell nanowires on top of individual GNRs as the top-gates for GNR field-effect transistors with ultrathin high-k dielectrics. The Si/HfO(2) core/shell nanowires are synthesized by atomic layer deposition of the HfO(2) shell on highly doped silicon nanowires with a precise control of the dielectric thickness down to 1-2 nm. Using the core/shell nanowires as the top-gates, high-performance GNR transistors have been achieved with transconductance reaching 3.2 mS microm(-1), the highest value for GNR transistors reported to date. This method, for the first time, demonstrates the effective integration of ultrathin high-k dielectrics with graphene with precisely controlled thickness and quality, representing an important step toward high-performance graphene electronics.