An all-solid-state, WDM silicon photonic digital link for chip-to-chip communications.

We describe a multiwavelength hybrid-integrated solid-state link on a 3 µm silicon-on-insulator (SOI) nanophotonic platform. The link spans three chips and employs germanium-silicon electroabsorption waveguide modulators, silicon transport waveguides, echelle gratings for multiplexing and demultiplexing, and pure germanium waveguide photo-detectors. The 8λ WDM Tx and Rx components are interconnected via a routing "bridge" chip using edge-coupled optical proximity communication. The packaged, retimed digital WDM link is demonstrated at 10 Gb/s and 10(-12) BER, with three wavelength channels consuming an on-chip power below 1.5 pJ/bit, excluding the external laser power.

Microring-based multi-chip WDM photonic module.

We report on a packaged prototype of a WDM photonic transceiver. It is an all-solid state hybrid assembly based on 130nm SOI photonic circuitry integrated with a 40nm CMOS VLSI driver. Our prototype supports eight tunable WDM channels operating at 10Gb/s, each capable of both transmitting and receiving data on the same chip. We discuss two options to close the link using the optical fiber or a waveguide bridge chip. We provide integration details and supporting link measurement data to describe packaged photonic module and its power efficient functionality with its on-chip power per channel averaging 1.3pJ/bit, excluding off-chip laser electrical power.

A high-speed, tunable silicon photonic ring modulator integrated with ultra-efficient active wavelength control.

We report the first complete 10G silicon photonic ring modulator with integrated ultra-efficient CMOS driver and closed-loop wavelength control. A selective substrate removal technique was used to improve the ring tuning efficiency. Limited by the thermal tuner driver output power, a maximum open-loop tuning range of about 4.5nm was measured with about 14mW of total tuning power including the heater driver circuit power consumption. Stable wavelength locking was achieved with a low-power mixed-signal closed-loop wavelength controller. An active wavelength tracking range of > 500GHz was demonstrated with controller energy cost of only 20fJ/bit.

Ultra-efficient 10 Gb/s hybrid integrated silicon photonic transmitter and receiver.

Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.