Benchtop and bedside validation of a low-cost programmable cortical stimulator in a testbed for bi-directional brain-computer-interface research.

Introduction: Bi-directional brain-computer interfaces (BD-BCI) to restore movement and sensation must achieve concurrent operation of recording and decoding of motor commands from the brain and stimulating the brain with somatosensory feedback. Methods: A custom programmable direct cortical stimulator (DCS) capable of eliciting artificial sensorimotor response was integrated into an embedded BCI system to form a safe, independent, wireless, and battery powered testbed to explore BD-BCI concepts at a low cost. The BD-BCI stimulator output was tested in phantom brain tissue by assessing its ability to deliver electrical stimulation equivalent to an FDA-approved commercial electrical cortical stimulator. Subsequently, the stimulator was tested in an epilepsy patient with subcortical electrocorticographic (ECoG) implants covering the sensorimotor cortex to assess its ability to elicit equivalent responses as the FDA-approved counterpart. Additional safety features (impedance monitoring, artifact mitigation, and passive and active charge balancing mechanisms) were also implemeneted and tested in phantom brain tissue. Finally, concurrent operation with interleaved stimulation and BCI decoding was tested in a phantom brain as a proof-of-concept operation of BD-BCI system. Results: The benchtop prototype BD-BCI stimulator's basic output features (current amplitude, pulse frequency, pulse width, train duration) were validated by demonstrating the output-equivalency to an FDA-approved commercial cortical electrical stimulator (R 2 > 0.99). Charge-neutral stimulation was demonstrated with pulse-width modulation-based correction algorithm preventing steady state voltage deviation. Artifact mitigation achieved a 64.5% peak voltage reduction. Highly accurate impedance monitoring was achieved with R 2 > 0.99 between measured and actual impedance, which in-turn enabled accurate charge density monitoring. An online BCI decoding accuracy of 93.2% between instructional cues and decoded states was achieved while delivering interleaved stimulation. The brain stimulation mapping via ECoG grids in an epilepsy patient showed that the two stimulators elicit equivalent responses. Significance: This study demonstrates clinical validation of a fully-programmable electrical stimulator, integrated into an embedded BCI system. This low-cost BD-BCI system is safe and readily applicable as a testbed for BD-BCI research. In particular, it provides an all-inclusive hardware platform that approximates the limitations in a near-future implantable BD-BCI. This successful benchtop/human validation of the programmable electrical stimulator in a BD-BCI system is a critical milestone toward fully-implantable BD-BCI systems.

A Fully-Integrated 1µW/Channel Dual-Mode Neural Data Acquisition System for Implantable Brain-Machine Interfaces.

This paper presents an ultra-low power mixed-signal neural data acquisition (MSN-DAQ) system that enables a novel low-power hybrid-domain neural decoding architecture for implantable brain-machine interfaces with high channel count. Implemented in 180nm CMOS technology, the 32-channel custom chip operates at 1V supply voltage and achieves excellent performance including 1.07µW/channel, 2.37/5.62 NEF/PEF and 88dB common-mode rejection ratio (CMRR) with significant back-end power-saving advantage compared to prior works. The fabricated prototype was further evaluated with in vivo human tests at bedside, and its performance closely follows that of a commercial recording system.

An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces.

This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high- γ band (80-160 Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72× power reduction in the analog blocks and up to 50× potential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32-channel ultra-low power signal acquisition front-end is fabricated in 180 nm CMOS process with 0.8 V supply. This chip consumes 1.05  µW (0.205  µW for feature extraction only) power and occupies 0.245 [Formula: see text] die area per channel. The chip measurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). In-vivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing.

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 µW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 µV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 µW from 0.6 V supply with IRNoise of 2.3 µV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.