Free-space parallel multichip interconnection system.

A parallel data-communication scheme is described for interchip communication with free-space optics. We present a proof-of-concept and feasibility demonstration of a practical modular packaging approach in which free-space optical interconnect modules can be simply integrated on top of an electronic multichip module (MCM). Our packaging architecture is based on a modified folded 4-f imaging system that is implemented with off-the-shelf optics, conventional electronic packaging techniques, and passive assembly techniques to yield a potentially low-cost packaging solution. The prototype system, as built, supports 48 independent free-space channels with eight separate laser and detector chips, in which each chip consists of a one-dimensional array of 12 devices. All chips are assembled on a single ceramic carrier together with three silicon complementary metal-oxide semiconductor chips. Parallel optoelectronic (OE) free-space interconnections are demonstrated at a speed of 200 MHz. The system is compact at only 10 in.(3) (~164 cm(3)) and is scalable because it can easily accommodate additional chips as well as two-dimensional OE device arrays for increased interconnection density.

Cross talk and ghost talk in a microbeam free-space optical interconnect system with vertical-cavity surface-emitting lasers, microlenses, and metal-semiconductor-metal detectors.

A diffraction-based beam-propagation model is used to study optical cross talk in microbeam free-space optical interconnection (FSOI) systems. The system consists of VCSEL's, microlenses, and metal-semiconductor-metal (MSM) detectors, with the detectors modeled as amplitude gratings with low contrast ratio (based on experimental results). Different possible cross-talk sources are studied. Results show that, in an optimized system, the cross talk caused by diffractive scattering is not an issue. However, in such systems the principal reflection from a MSM detector surface creates two problems: VCSEL coupling and ghost talk. The coupling of the reflected beam into the VCSEL's may cause power oscillation (and increase the bit error rate), whereas ghost talk will limit the distance-bandwidth product of the interconnect system. This optical system is also abstracted in hspice together with the laser driver and receiver circuits to analyze ghost talk in this system. Results show that at high speed (1 Gbit/s or more) these effects negatively affect system performance.

Optomechanical design and characterization of a printed-circuit-board-based free-space optical interconnect package.

We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI's) can be integrated simply on electronic multichip modules (MCM's) for intra-MCM-board interconnects. Our system-level packaging architecture is based on a modified folded 4f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than -20 dB at low frequency have been measured. The system is compact at only 10 in.3 (25.4 cm3) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

Speed and energy analysis of digital interconnections: comparison of on-chip, off-chip, and free-space technologies.

We model and compare on-chip (up to wafer scale) and off-chip(multichip module) high-speed electrical interconnections withfree-space optical interconnections in terms of speed performance andenergy requirements for digital transmission in large-scalesystems. For all technologies the interconnections are firstmodeled and optimized for minimum delay as functions of theinterconnection length for both one-to-one and fan-outconnections. Then energy requirements are derived as functions ofthe interconnection length. Free-space optical interconnectionsthat use multiple-quantum-well modulators or vertical-cavitysurface-emitting lasers as transmitters are shown to offer aspeed-energy product advantage as high as 30 over that of the electrical interconnection technologies.

Computer-aided design for optoelectronic systems: introduction to the feature issue.

Welcome to the first special issue of Applied Optics on computer-aided design for optoelectronic systems. This special issue stemmed from our realization of the need for dialogue between optoelectronic system designers and computer-aided-design developers, as well as from the realization that various research groups are developing or, in some instances, have already developed and commercialized such tools. Our goal for this special issue is to enhance this type of dialogue by showing to the optoelectronic system design community the current state of optoelectronic computer-aided-design tools.

Chatoyant: a computer-aided- design tool for free-space optoelectronic systems.

Chatoyant is a tool for the simulation and the analysis of heterogeneous free-space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoelectronic devices and results that demonstrate the system's ability to predict the effects of various component parameters, such as detector geometry, and system parameters, such as alignment tolerances, on system-performance measures, such as the bit-error rate.

Small-signal-equivalent circuits for a semiconductor laser.

Passive electrical circuits whose voltage and current equations are exactly equivalent to the small-signal rate equations of a semiconductor laser are derived to model an electrically modulated laser (verified to be the same as that given in the literature), an optically modulated laser (i.e., a laser used as an optical amplifier), and a multimode laser. These circuits offer a fast and efficient simulation tool with little computational complexity in which the small-signal assumption (i.e., small modulation range) is neither violated nor insufficient for the simulation.

Photorefractive Beam splitter for Free-Space Optical Interconnections.

A photorefractive beam splitter (PRBS) is introduced as an alternative to a polarizing beam splitter (PBS) for coupling optical power into reflective modulators in a free-space optical interconnection system. The PRBS uses a single diffraction grating recorded in a photorefractive material to redirect the incident laser light into the first diffraction order and onto the modulators. Reflected interconnection light not matching the Bragg angle criteria transmits uncoupled through the beam splitter. Experimental results show that the PRBS provides better, more uniform transmission for off-axis beams than the currently used PBS.

Motionless-head parallel-readout optical-disk system: experimental results.

The motionless-head parallel-readout optical-disk system is designed to read out two-dimensional bit planes that are stored as one-dimensional Fourier-transform computer-generated holograms distributed radially on the disk active surface. Such a system, when built at full scale, could offer several potential advantages: high data-transfer rates of 1 Gbyte/s and higher, low access times of less than 15 ms, low retrieval times (the time required to read the entire memory) of less than 25 ms, and simple optical implementation. The experimental results of a scaled-down implementation of the system are presented.

Photonic content-addressable memory system that uses a parallel-readout optical disk.

We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 × 128 bit images and also on variable-size subimages. The system's behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.

Motionless-head parallel readout optical-disk system.

The design, analysis, and feasibility of a novel motionless-head parallel readout optical-disk system are presented. The system is designed to read data blocks distributed radially on the disk's active surface, and it has the unique advantage that no mechanical motion of the head is required for fast access, focusing, or tracking. Data access is achieved solely through the disk rotation, and the entire memory can be read in one rotation. In principle, this permits a data rate of up to 1 Gbyte/s. The data blocks are one-dimensional Fourier-transform computer-generated holograms, each reconstructing one column of a two-dimensional output image. Owing to the information redundancy and shift invariance properties of Fourier-transform holograms, tracking and focusing servo requirements are eliminated. A holographic encoding method is developed to produce high signal-to-noise ratio reconstructions and to reduce significantly the radial alignment requirements of the recorded data bits. The optical readout system consists of only three cylindrical lenses. Two of these may be replaced by a single hybrid diffractive-refractive optical element for easier system alignment and better optical performance, i.e., reduced aberrations and improved resolution. The throughputs and retrieval times of this parallel readout optical-disk system make it well suited to a variety of parallel computing architectures, including a high-performance optoelectronic associative memory [Proc. Soc. Photo-Opt. Instrum. Eng. 1347, 86 (1990)].

Grain-size considerations for optoelectronic multistage interconnection networks.

This paper investigates, at the system level, the performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 x 2 switches or grains to be generalized to larger K x K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of log(k) N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input-output. The system design use an effi ient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 x 256 result in a reduced performance, while grain sizes smaller than 16 x 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250-400 electronic transistors per optical input-output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost functions mentioned above. As VLSI minimum feature sizes decrease, the optimum grain size increases, whereas, if optical interconnect performance in terms of the detector power or modulator driving voltage requirements improves, the optimum grain size may be reduced. Finally, several architectural modifications to the system, such as K x K contention-free switches and sorting networks, are investigated and optimized for grain size. Results indicate that system bandwidth can be increased, but at the price of reduced performance/cost. The optoelectronic MIN architectures considered thus provide a broad range of performance/cost alternatives and offer a superior performance over purely electronic MIN's.