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1.
Adv Sci (Weinh) ; : e2309264, 2024 Jun 03.
Artigo em Inglês | MEDLINE | ID: mdl-38828782

RESUMO

Se alloying has enabled significantly higher carrier lifetimes and photocurrents in CdTe solar cells, but these benefits can be highly dependent on CdSexTe1-x processing. This work evaluates the optoelectronic, chemical, and electronic properties of thick (3 µm) undoped CdSexTe1-x of uniform composition and varied processing conditions (CdSexTe1-x evaporation rate, CdCl2 anneal, Se content) chosen to reflect various standard device processing conditions. Sub-bandgap defect emission is observed, which increased as Se content increased and with "GrV-optimized CdCl2" (i.e., CdCl2 anneal conditions used for group-V-doped devices). Low carrier lifetime is found for GrV-optimized CdCl2, slow CdSexTe1-x deposition, and low-Se films. Interestingly, all films (including CdTe control) exhibited n-type behavior, where electron density increased with Se up to an estimated ≈1017 cm-3. This behavior appears to originate during the CdCl2 anneal, possibly from Se diffusion leading to anion vacancy (e.g., VSe, VTe) and ClTe generation.

2.
ACS Appl Mater Interfaces ; 11(13): 13003-13010, 2019 Apr 03.
Artigo em Inglês | MEDLINE | ID: mdl-30848583

RESUMO

Interfaces at the front of superstrate CdTe-based solar cells are critical to carrier transport, recombination, and device performance, yet determination of the chemical structure of these nanoscale regions has remained elusive. This is partly due to changes that occur at the front interfaces during high temperature growth and substantive changes occurring during postdeposition processing. In addition, these buried interfaces are extremely difficult to access in a way that preserves chemical information. In this work, we use a recently developed thermomechanical cleaving technique paired with X-ray photoelectron spectroscopy to probe oxidation states at the SnO2 interface of CdTe solar cells. We show that the tin oxide front electrode promotes the formation of nanometer-scale oxides of tellurium and sulfur. Most oxidation occurs during CdCl2/O2 activation. Surprisingly, we show that relatively low-temperature anneals (180-260 °C) used to diffuse and activate copper acceptors in a doping/back contact process also cause significant changes in oxidation at the front of the cell, providing a heretofore missing aspect of how back contact processes can modify device transport, recombination, and performance. Device performance is shown to correlate with the extent of tellurium and sulfur oxidation within this nanometer-scale region. Mechanisms responsible for these beneficial effects are proposed.

3.
ACS Appl Mater Interfaces ; 10(51): 44854-44861, 2018 Dec 26.
Artigo em Inglês | MEDLINE | ID: mdl-30488692

RESUMO

Controlled delamination of thin-film photovoltaics (PV) post-growth can reveal interfaces that are critical to device performance yet are poorly understood because of their inaccessibility within the device stack. In this work, we demonstrate a technique to lift off thin-film solar cells from their glass substrates in a clean, reproducible manner by first laminating a polymeric backsheet to the device and then thermally shocking the system at low temperatures ( T ≤ -30 °C). To enable clean delamination of diverse thin-film architectures, a theoretical framework is developed and key process control parameters are identified. Focusing on cadmium telluride (CdTe) devices, we show that the lamination temperature and device architecture control the quality of lift-off, while the rate at which the film stack is removed is controlled by the delamination temperature. Crack-free CdTe devices are removed and successfully recontacted, recovering up to 80% of the original device efficiency. The areal density of these devices is ∼0.4 kg m-2, a reduction of over an order of magnitude relative to their initial weight on glass. The framework developed here provides a pathway toward both the development of inexpensive, flexible PV with high specific power and the study of previously buried interfaces in thin-film architectures.

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