Sequentially Vapor-Grown Hybrid Perovskite for Planar Heterojunction Solar Cells.

High-quality and reproducible perovskite layer fabrication routes are essential for the implementation of efficient planar solar cells. Here, we introduce a sequential vapor-processing route based on physical vacuum evaporation of a PbCl2 layer followed by chemical reaction with methyl-ammonium iodide vapor. The demonstrated vapor-grown perovskite layers show compact, pinhole-free, and uniform microstructure with the average grain size of ~ 320 nm. Planar heterojunction perovskite solar cells are fabricated using TiO2 and spiro-OMeTAD charge transporting layers in regular n-i-p form. The devices exhibit the best efficiency of 11.5% with small deviation indicating the high uniformity and reproducibility of the perovskite layers formed by this route.

Evaluating the Optoelectronic Quality of Hybrid Perovskites by Conductive Atomic Force Microscopy with Noise Spectroscopy.

Organic-inorganic hybrid perovskite solar cells have emerged as promising candidates for next-generation solar cells. To attain high photovoltaic efficiency, reducing the defects in perovskites is crucial along with a uniform coating of the films. Also, evaluating the quality of synthesized perovskites via facile and adequate methods is important as well. Herein, CH3NH3PbI3 perovskites were synthesized by applying second solvent dripping to nonstoichiometric precursors containing excess CH3NH3I. The resulting perovskite films exhibited a larger average grain size with a better crystallinity compared to that from stoichiometric precursors. As a result, the performance of planar perovskite solar cells was significantly improved, achieving an efficiency of 14.3%. Furthermore, perovskite films were effectively analyzed using a conductive AFM and noise spectroscopy, which have been uncommon in the field of perovskite solar cells. Comparing the topography and photocurrent maps, the variation of photocurrents in nanoscale was systematically investigated, and a linear relationship between the grain size and photocurrent was revealed. Also, noise analyses with a conductive probe enabled examination of the defect density of perovskites at specific grain interiors by excluding the grain-boundary effect, and reduced defects were clearly observed for the perovskites using CH3NH3I-rich precursors.

Improving scattering layer through mixture of nanoporous spheres and nanoparticles in ZnO-based dye-sensitized solar cells.

A scattering layer is utilized by mixing nanoporous spheres and nanoparticles in ZnO-based dye-sensitized solar cells. Hundred-nanometer-sized ZnO spheres consisting of approximately 35-nm-sized nanoparticles provide not only effective light scattering but also a large surface area. Furthermore, ZnO nanoparticles are added to the scattering layer to facilitate charge transport and increase the surface area as filling up large voids. The mixed scattering layer of nanoparticles and nanoporous spheres on top of the nanoparticle-based electrode (bilayer geometry) improves solar cell efficiency by enhancing both the short-circuit current (J sc) and fill factor (FF), compared to the layer consisting of only nanoparticles or nanoporous spheres.

Si-nanowire-array-based NOT-logic circuits constructed on plastic substrates using top-down methods.

Si-nanowire (NW)-array-based NOT-logic circuits were constructed on plastic substrates. The Si-NW arrays were fabricated on a Si wafer through top-down methods, including conventional photolithography and crystallographic wet etching, and transferred onto the plastic substrates. Two field-effect transistors were fabricated on a single Si-NW array composed of five nanowires aligned in parallel and connected in series to form NOT-logic circuits. The excellent flexibility of the fabricated device was confirmed by bending-cycling tests. The voltage-transfer curve of the NOT-logic circuits showed an inverting operation with a logic swing of -92% and voltage gain of -2.5.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Investigation on light emission in light-emitting diodes constructed with n-ZnO and p-Si nanowires.

The light emission was investigated in light-emitting diodes (LEDs) constructed with n-ZnO and p-Si nanowires (NWs). ZnO NWs were synthesized by thermal chemical vapor deposition and Si NWs were formed by crystallographic wet etching of a Si wafer. The LEDs were fabricated using the NWs via dielectrophoresis (DEP) and direct transfer methods. The DEP method enabled to align the ZnO NW at the position that led to p-n heterojunction diodes by crossing with the transferred Si NW. The I-V curve of the p-n heterojunction diode showed the well-defined current-rectifying characteristic, with a turn-on voltage of 3 V. The electroluminescence spectrum in the dark showed the strong emission at approximately 385 nm and the broad emission centered at approximately 510 nm, at a forward bias of 30 V. Under the illumination of 325-nm-wavelength light, the luminescence intensity at 385 nm was dramatically enhanced, compared to that in the dark, probably due to the electric-field-induced enhancement of luminescence.

Flexible logic gates composed of high performance GaAs-nanowire-based MESFETs with MHz-dynamic operations.

High performance NOT, NAND and NOR logic gates composed of GaAs-nanowire (NW)-based metal-semiconductor field-effect transistors (MESFETs) were constructed on flexible plastics through a noble top-down route. The representative GaAs-NW-based MESFETs exhibited superior electrical characteristics such as a high mobility (∼3300 cm(2) V(-) s(-1)), large I(on)/I(off) ratio (∼10(8)) and small subthreshold swing (∼70 mV/dec). The NOT, NAND and NOR logic gates showed a maximum voltage gain of 108 and logic swings of 97-99%. All of the logic gates successfully retained their electrical characteristics during 2000 bending cycles. Furthermore, the logic gates were well operated by square-wave signals of up to 100 MHz under various strain conditions. The high performances demonstrated in this study open the way to the realization of high speed flexible logic devices.

Si-based flexible memristive systems constructed using top-down methods.

Si-based memristive systems consisting of Ag, amorphous Si, and heavily doped p-type Si nanowires were successfully constructed on plastic substrates through top-down methods, including the crystallographic wet etching of Si wafers, transfer onto plastic substrates, and thin film patterning. The memristive systems showed excellent memory characteristics and flexibility, such as intrinsic hysteric and rectifying behaviors, on/off resistance ratios of >1 × 10(5), and durability for up to 1000 bending cycles. The correlations between the Ag-filament-related nanostructures formed in amorphous Si and the resistance-switching behaviors were carefully examined with the tunneling current model, transmission electron microscopy, and secondary ion mass spectroscopy to explore the switching mechanism. Our study suggests the promising potential of the Si-based memristive systems for the development of next-generation flexible nonvolatile memory.

Electrically driven lasing in light-emitting devices composed of n-ZnO and p-Si nanowires.

Electrically driven lasing was demonstrated in light-emitting devices composed of n-ZnO and p-Si nanowires (NWs). The ZnO NWs were synthesized by thermal chemical vapor deposition and the Si NWs were formed by crystallographic wet etching of a Si wafer. The p-n heterojunction devices were constructed using the NWs by the direct transfer and dielectrophoresis methods. At an excitation current of 2 µA, the electroluminescence spectrum showed lasing behavior, and this phenomenon was explained by the ZnO-nanostructure-related cavity property.

Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS Inverters on plastic.

A route to the top-down fabrication of highly ordered and aligned silicon nanowire (SiNW) arrays with degenerately doped source/drain regions from a bulk Si wafer is presented. In this approach, freestanding n- and p-SiNWs with an inverted triangular cross section are obtained using conventional photolithography, crystal orientation dependent wet etching, size reduction oxidation, and ion implantation doping. Based on these n- and p-SiNWs transferred onto a plastic substrate, simple SiNW-based complementary metal-oxide-semiconductor (CMOS) inverters are constructed for the possible applications of these SiNW arrays in integrated circuits on plastic. The static voltage transfer characteristic of the SiNW-based CMOS inverter exhibits a voltage gain of ∼9 V/V and a transition of 0.32 V at an operating voltage of 1.5 V with a full output voltage swing between 0 V and V(DD), and its mechnical bendability indicates good fatigue properties for potential applications of flexible electronics. This novel top-down approach is fully compatible with the current state-of-the-art Si-based CMOS technologies and, therefore, offers greater flexibility in device design for both high-performance and low-power functionality.