Analytical modelling of the transport in analog filamentary conductive-metal-oxide/HfOx ReRAM devices.

The recent co-optimization of memristive technologies and programming algorithms enabled neural networks training with in-memory computing systems. In this context, novel analog filamentary conductive-metal-oxide (CMO)/HfOx redox-based resistive switching memory (ReRAM) represents a key technology. Despite device performance enhancements reported in literature, the underlying mechanism behind resistive switching is not fully understood. This work presents the first physics-based analytical model of the current transport and of the resistive switching in these devices. As a case study, analog TaOx/HfOx ReRAM devices are considered. The current transport is explained by a trap-to-trap tunneling process, and the resistive switching by a modulation of the defect density within the sub-band of the TaOx that behaves as electric field and temperature confinement layer. The local temperature and electric field distributions are derived from the solution of the electric and heat transport equations in a 3D finite element ReRAM model. The intermediate resistive states are described as a gradual modulation of the TaOx defect density, which results in a variation of its electrical conductivity. The drift-dynamics of ions during the resistive switching is analytically described, allowing the estimation of defect migration energies in the TaOx layer. Moreover, the role of the electro-thermal properties of the CMO layer is unveiled. The proposed analytical model accurately describes the experimental switching characteristic of analog TaOx/HfOx ReRAM devices, increasing the physical understanding and providing the equations necessary for circuit simulations incorporating this technology.

Analog Resistive Switching Devices for Training Deep Neural Networks with the Novel Tiki-Taka Algorithm.

A critical bottleneck for the training of large neural networks (NNs) is communication with off-chip memory. A promising mitigation effort consists of integrating crossbar arrays of analogue memories in the Back-End-Of-Line, to store the NN parameters and efficiently perform the required synaptic operations. The "Tiki-Taka" algorithm was developed to facilitate NN training in the presence of device nonidealities. However, so far, a resistive switching device exhibiting all the fundamental Tiki-Taka requirements, which are many programmable states, a centered symmetry point, and low programming noise, was not yet demonstrated. Here, a complementary metal-oxide semiconductor (CMOS)-compatible resistive random access memory (RRAM), showing more than 30 programmable states with low noise and a symmetry point with only 5% skew from the center, is presented for the first time. These results enable generalization of Tiki-Taka training from small fully connected networks to larger long-/short-term-memory types of NN.

A multi-timescale synaptic weight based on ferroelectric hafnium zirconium oxide.

Brain-inspired computing emerged as a forefront technology to harness the growing amount of data generated in an increasingly connected society. The complex dynamics involving short- and long-term memory are key to the undisputed performance of biological neural networks. Here, we report on sub-µm-sized artificial synaptic weights exploiting a combination of a ferroelectric space charge effect and oxidation state modulation in the oxide channel of a ferroelectric field effect transistor. They lead to a quasi-continuous resistance tuning of the synapse by a factor of 60 and a fine-grained weight update of more than 200 resistance values. We leverage a fast, saturating ferroelectric effect and a slow, ionic drift and diffusion process to engineer a multi-timescale artificial synapse. Our device demonstrates an endurance of more than 10 10 cycles, a ferroelectric retention of more than 10 years, and various types of volatility behavior on distinct timescales, making it well suited for neuromorphic and cognitive computing.

Neuromorphic Systems Design by Matching Inductive Biases to Hardware Constraints.

Neuromorphic systems are designed with careful consideration of the physical properties of the computational substrate they use. Neuromorphic engineers often exploit physical phenomena to directly implement a desired functionality, enabled by "the isomorphism between physical processes in different media" (Douglas et al., 1995). This bottom-up design methodology could be described as matching computational primitives to physical phenomena. In this paper, we propose a top-down counterpart to the bottom-up approach to neuromorphic design. Our top-down approach, termed "bias matching," is to match the inductive biases required in a learning system to the hardware constraints of its implementation; a well-known example is enforcing translation equivariance in a neural network by tying weights (replacing vector-matrix multiplications with convolutions), which reduces memory requirements. We give numerous examples from the literature and explain how they can be understood from this perspective. Furthermore, we propose novel network designs based on this approach in the context of collaborative filtering. Our simulation results underline our central conclusions: additional hardware constraints can improve the predictions of a Machine Learning system, and understanding the inductive biases that underlie these performance gains can be useful in finding applications for a given constraint.

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights.

Neuromorphic computing architectures enable the dense colocation of memory and processing elements within a single circuit. This colocation removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are nonvolatile synaptic elements such as memristors. Key memristor properties include a suitable nonvolatile resistance range, continuous linear resistance modulation, and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf0.57Zr0.43O2 (HZO) field-effect transistor (FeFET) with good linearity. Our FeFET operates with low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been performed over 4 bit depth with low noise (1%) in the tungsten oxide (WOx) readout channel. By adjusting the channel thickness from 15 to 8 nm, the on/off ratio of the FeFET can be engineered from 1 to 200% with an on-resistance ideally >100 kΩ, depending on the channel geometry. The device concept is using earth-abundant materials and is compatible with a back end of line (BEOL) integration into complementary metal-oxide-semiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high-density, large-scale integrated arrays of artificial analog synapses.

Polymer waveguides for electro-optical integration in data centers and high-performance computers.

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

Flip-chip optical couplers with scalable I/O count for silicon photonics.

A scalable and tolerant optical interfacing method based on flip-chip bonding is developed for silicon photonics packaging. Bidirectional optical couplers between multiple silicon-on-insulator waveguides and single-mode polymer waveguides are designed and fabricated. Successful operation is verified experimentally in the 1530-1570 nm spectral window. At the wavelength of 1570 nm, the coupling loss is as low as 0.8 dB for both polarization states and the planar misalignment loss is less than 0.6 dB for TE and 0.3 dB for TM polarization in a lateral silicon-polymer waveguide offset range of ± 2 µm. The coupling loss does not exhibit any temperature dependence up to the highest measurement point of 70°C.

Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing.

We present 1-to-8 wavelength (de-)multiplexer devices based on a binary tree of cascaded Mach-Zehnder-like lattice filters, and manufactured using a 90 nm CMOS-integrated silicon photonics technology. We demonstrate that these devices combine a flat pass-band over more than 50% of the channel spacing with low insertion loss of less than 1.6 dB, and have a small device size of approximately 500 × 400 µm. This makes this type of filters well suited for application as WDM (de-)multiplexer in silicon photonics transceivers for optical data communication in large scale computer systems.

A strong electro-optically active lead-free ferroelectric integrated on silicon.

The development of silicon photonics could greatly benefit from the linear electro-optical properties, absent in bulk silicon, of ferroelectric oxides, as a novel way to seamlessly connect the electrical and optical domain. Of all oxides, barium titanate exhibits one of the largest linear electro-optical coefficients, which has however not yet been explored for thin films on silicon. Here we report on the electro-optical properties of thin barium titanate films epitaxially grown on silicon substrates. We extract a large effective Pockels coefficient of r(eff) = 148 pm V(-1), which is five times larger than in the current standard material for electro-optical devices, lithium niobate. We also reveal the tensor nature of the electro-optical properties, as necessary for properly designing future devices, and furthermore unambiguously demonstrate the presence of ferroelectricity. The integration of electro-optical active films on silicon could pave the way towards power-efficient, ultra-compact integrated devices, such as modulators, tuning elements and bistable switches.

A single InP-on-SOI microdisk for high-speed half-duplex on-chip optical links.

We demonstrate for the first time that a single compact, electrically contacted indium phosphide based microdisk heterogeneously integrated on a silicon-on-insulator waveguide can be used as both a high-speed modulator and photo detector. We demonstrate high-speed operation up to 10 Gb/s and present bit-error rate results of both operation modes.

A low-power high-speed InP microdisk modulator heterogeneously integrated on a SOI waveguide.

We report on the modulation characteristics of indium phosphide (InP) based microdisks heterogeneously integrated on a silicon-on-insulator (SOI) waveguide. We present static extinction ratios and dynamic operation up to 10 Gb/s. Operation with a bit-error rate below 1 × 10(-9) is demonstrated at 2.5, 5.0 and 10.0 Gb/s and the performance is compared with that of a commercial modulator. Power penalties are analyzed with respect to the pattern length. The power consumption is calculated and compared with state-of-the-art integrated modulator concepts. We demonstrate that InP microdisk modulators combine low-power and low-voltage operation with low footprint and high-speed. Moreover, the devices can be fabricated using the same technology as for lasers, detectors and wavelength converters, making them very attractive for co-integration.

Ultrafast all-optical modulator with femtojoule absorbed switching energy in silicon-on-insulator.

We demonstrate an all-optical switch based on a waveguide-embedded 1D photonic crystal cavity fabricated in silicon-on-insulator technology. Light at the telecom wavelength is modulated at high-speed by control pulses in the near infrared, harnessing the plasma dispersion effect. The actual absorbed switching power required for a 3 dB modulation depth is measured to be as low as 6 fJ. While the switch-on time is on the order of a few picoseconds, the relaxation time is almost 500 ps and limited by the lifetime of the charge carriers.

Circular grating resonators as small mode-volume microcavities for switching.

We demonstrate the suitability of microcavities based on circular grating resonators (CGRs) as fast switches. This type of optical resonator is characterized by a high quality factor and very small mode volume. The waveguide-coupled CGRs are fabricated with silicon-on-insulator technology compatible with standard complementary metal-oxide semiconductor (CMOS) processing. The linear optical properties of the CGRs are investigated by transmission spectroscopy. From 3D finite-difference time-domain simulations of isolated CGRs, we identify the measured resonances. We probe the spatial distribution and the parasitic losses of a resonant optical mode with scanning near-field optical microscopy. We observe fast all-optical switching within a few picoseconds by optically generating free charge carriers within the cavity.