Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs Lifetime by Reliability Tests.

High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non irradiated devices and those which survived to the neutron irradiation tests, with neutron fluence up to 2× 1011 (n/cm2). Electrical characterization performed pre and post-irradiation on different part number of power devices (Si, SiC MOSFETs and IGBTs) which survived to neutron irradiation tests does not show alteration of the data-sheet electrical parameters due to neutron interaction with the device.

Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons.

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed.