RESUMO
Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current (IMIN) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of IMIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.
RESUMO
The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO2 film with a metallic carbon nanotube as a nanoscale heater, without using an external capacitor. Compared with VO2-only devices, adding the nanotube heater dramatically decreases the transient duration and pulse energy, and increases the spiking frequency, by up to 3 orders of magnitude. This is caused by heating and cooling of the VO2 across its insulator-metal transition being localized to a nanoscale conduction channel in an otherwise bulk medium. This result provides an important component of energy-efficient neuromorphic computing systems and a lithography-free technique for energy-scaling of electronic devices that operate via bulk mechanisms.
RESUMO
Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (â¼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.
