RESUMO
Molybdenum trioxide (MoO3), an important transition metal oxide (TMO), has been extensively investigated over the past few decades due to its potential in existing and emerging technologies, including catalysis, energy and data storage, electrochromic devices, and sensors. Recently, the growing interest in two-dimensional (2D) materials, often rich in interesting properties and functionalities compared to their bulk counterparts, has led to the investigation of 2D MoO3. However, the realization of large-area true 2D (single to few atom layers thick) MoO3 is yet to be achieved. Here, we demonstrate a facile route to obtain wafer-scale monolayer amorphous MoO3 using 2D MoS2 as a starting material, followed by UV-ozone oxidation at a substrate temperature as low as 120 °C. This simple yet effective process yields smooth, continuous, uniform, and stable monolayer oxide with wafer-scale homogeneity, as confirmed by several characterization techniques, including atomic force microscopy, numerous spectroscopy methods, and scanning transmission electron microscopy. Furthermore, using the subnanometer MoO3 as the active layer sandwiched between two metal electrodes, we demonstrate the thinnest oxide-based nonvolatile resistive switching memory with a low voltage operation and a high ON/OFF ratio. These results (potentially extendable to other TMOs) will enable further exploration of subnanometer stoichiometric MoO3, extending the frontiers of ultrathin flexible oxide materials and devices.
RESUMO
2D materials with low-temperature processing hold promise for electronic devices that augment conventional silicon technology. To meet this promise, devices should have capabilities not easily achieved with silicon technology, including planar fully-depleted silicon-on-insulator with substrate body-bias, or vertical finFETs with no body-bias capability. In this work, we fabricate and characterize a device [a double-gate MoS2 field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG)] in multiple operating conditions to demonstrate logic, memory, and synaptic applications; a range of h-BN thicknesses is investigated for charge retention in the FG. In particular, we demonstrate this device as a (i) logic FET with adjustable VT by charges stored in the FG, (ii) digital flash memory with lower pass-through voltage to enable improved reliability, and (iii) synaptic device with decoupling of tunneling and gate dielectrics to achieve a symmetric program/erase conductance change. Overall, this versatile device, compatible to back-end-of-line integration, could readily augment silicon technology.