Hysteresis in memristors produces conduction inductance and conduction capacitance effects.

Memristors are devices in which the conductance state can be alternately switched between a high and a low value by means of a voltage scan. In general, systems involving a chemical inductor mechanism as solar cells, asymmetric nanopores in electrochemical cells, transistors, and solid state memristive devices, exhibit a current increase and decrease over time that generates hysteresis. By performing small signal ac impedance spectroscopy, we show that memristors, or any other system with hysteresis relying on the conductance modulation effect, display intrinsic dynamic inductor-like and capacitance-like behaviours in specific input voltage ranges. Both the conduction inductance and the conduction capacitance originate in the same delayed conduction process linked to the memristor dynamics and not in electromagnetic or polarization effects. A simple memristor model reproduces the main features of the transition from capacitive to inductive impedance spectroscopy spectra, which causes a nonzero crossing of current-voltage curves.

Thermal Compact Modeling and Resistive Switching Analysis in Titanium Oxide-Based Memristors.

Resistive switching devices based on the Au/Ti/TiO2/Au stack were developed. In addition to standard electrical characterization by means of I-V curves, scanning thermal microscopy was employed to localize the hot spots on the top device surface (linked to conductive nanofilaments, CNFs) and perform in-operando tracking of temperature in such spots. In this way, electrical and thermal responses can be simultaneously recorded and related to each other. In a complementary way, a model for device simulation (based on COMSOL Multiphysics) was implemented in order to link the measured temperature to simulated device temperature maps. The data obtained were employed to calculate the thermal resistance to be used in compact models, such as the Stanford model, for circuit simulation. The thermal resistance extraction technique presented in this work is based on electrical and thermal measurements instead of being indirectly supported by a single fitting of the electrical response (using just I-V curves), as usual. Besides, the set and reset voltages were calculated from the complete I-V curve resistive switching series through different automatic numerical methods to assess the device variability. The series resistance was also obtained from experimental measurements, whose value is also incorporated into a compact model enhanced version.

Hardware implementation of memristor-based artificial neural networks.

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Thermal Characterization of Conductive Filaments in Unipolar Resistive Memories.

A methodology to estimate the device temperature in resistive random access memories (RRAMs) is presented. Unipolar devices, which are known to be highly influenced by thermal effects in their resistive switching operation, are employed to develop the technique. A 3D RRAM simulator is used to fit experimental data and obtain the maximum and average temperatures of the conductive filaments (CFs) that are responsible for the switching behavior. It is found that the experimental CFs temperature corresponds to the maximum simulated temperatures obtained at the narrowest sections of the CFs. These temperature values can be used to improve compact models for circuit simulation purposes.

Hybrid 2D-CMOS microchips for memristive applications.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2-Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D-CMOS hybrid microchips for memristive applications-CMOS stands for complementary metal-oxide-semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

Memristive technologies for data storage, computation, encryption, and radio-frequency communication.

Memristive devices, which combine a resistor with memory functions such that voltage pulses can change their resistance (and hence their memory state) in a nonvolatile manner, are beginning to be implemented in integrated circuits for memory applications. However, memristive devices could have applications in many other technologies, such as non-von Neumann in-memory computing in crossbar arrays, random number generation for data security, and radio-frequency switches for mobile communications. Progress toward the integration of memristive devices in commercial solid-state electronic circuits and other potential applications will depend on performance and reliability challenges that still need to be addressed, as described here.

On the Thermal Models for Resistive Random Access Memory Circuit Simulation.

Resistive Random Access Memories (RRAMs) are based on resistive switching (RS) operation and exhibit a set of technological features that make them ideal candidates for applications related to non-volatile memories, neuromorphic computing and hardware cryptography. For the full industrial development of these devices different simulation tools and compact models are needed in order to allow computer-aided design, both at the device and circuit levels. Most of the different RRAM models presented so far in the literature deal with temperature effects since the physical mechanisms behind RS are thermally activated; therefore, an exhaustive description of these effects is essential. As far as we know, no revision papers on thermal models have been published yet; and that is why we deal with this issue here. Using the heat equation as the starting point, we describe the details of its numerical solution for a conventional RRAM structure and, later on, present models of different complexity to integrate thermal effects in complete compact models that account for the kinetics of the chemical reactions behind resistive switching and the current calculation. In particular, we have accounted for different conductive filament geometries, operation regimes, filament lateral heat losses, the use of several temperatures to characterize each conductive filament, among other issues. A 3D numerical solution of the heat equation within a complete RRAM simulator was also taken into account. A general memristor model is also formulated accounting for temperature as one of the state variables to describe electron device operation. In addition, to widen the view from different perspectives, we deal with a thermal model contextualized within the quantum point contact formalism. In this manner, the temperature can be accounted for the description of quantum effects in the RRAM charge transport mechanisms. Finally, the thermometry of conducting filaments and the corresponding models considering different dielectric materials are tackled in depth.

In Situ Observation of Low-Power Nano-Synaptic Response in Graphene Oxide Using Conductive Atomic Force Microscopy.

Multiple studies have reported the observation of electro-synaptic response in different metal/insulator/metal devices. However, most of them analyzed large (>1 µm2 ) devices that do not meet the integration density required by industry (1010  devices/mm2 ). Some studies emploied a scanning tunneling microscope (STM) to explore nano-synaptic response in different materials, but in this setup there is a nanogap between the insulator and one of the metallic electrodes (i.e., the STM tip), not present in real devices. Here, it is demonstrated how to use conductive atomic force microscopy to explore the presence and quality of nano-synaptic response in confined areas <50 nm2 . Graphene oxide (GO) is selected due to its easy fabrication. Metal/GO/metal nano-synapses exhibit potentiation and paired pulse facilitation with low write current levels <1 µA (i.e., power consumption ≈3 µW), controllable excitatory post-synaptic currents, and long-term potentiation and depression. The results provide a new method to explore nano-synaptic plasticity at the nanoscale, and point to GO as an important candidate for the fabrication of ultrasmall (<50 nm2 ) electronic synapses fulfilling the integration density requirements of neuromorphic systems.

Advanced Data Encryption ​using 2D Materials.

Advanced data encryption requires the use of true random number generators (TRNGs) to produce unpredictable sequences of bits. TRNG circuits with high degree of randomness and low power consumption may be fabricated by using the random telegraph noise (RTN) current signals produced by polarized metal/insulator/metal (MIM) devices as entropy source. However, the RTN signals produced by MIM devices made of traditional insulators, i.e., transition metal oxides like HfO2 and Al2 O3 , are not stable enough due to the formation and lateral expansion of defect clusters, resulting in undesired current fluctuations and the disappearance of the RTN effect. Here, the fabrication of highly stable TRNG circuits with low power consumption, high degree of randomness (even for a long string of 224  - 1 bits), and high throughput of 1 Mbit s-1 by using MIM devices made of multilayer hexagonal boron nitride (h-BN) is shown. Their application is also demonstrated to produce one-time passwords, which is ideal for the internet-of-everything. The superior stability of the h-BN-based TRNG is related to the presence of few-atoms-wide defects embedded within the layered and crystalline structure of the h-BN stack, which produces a confinement effect that avoids their lateral expansion and results in stable operation.