Content-Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing.

As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.

Low-Thermal-Budget Ferroelectric Field-Effect Transistors Based on CuInP2S6 and InZnO.

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of ∼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.

Strong Temperature Effect on the Ferroelectric Properties of CuInP2S6 and Its Heterostructures.

Van der Waals (vdW) ferroelectric insulator CuInP2S6 (CIPS) has attracted intense research interest due to its unique ferroelectric and piezoelectric properties. In this paper, we systematically investigate the temperature and frequency dependence of the ferroelectric properties of CIPS. We find that there is a large imprint in the CIPS capacitor, which can be attributed to the fixed dipoles induced by defects. At high temperatures and low frequencies, the amplitude and direction of the imprint become tunable by the preset pulse, as the copper ions are more mobile and these dipoles become switchable. When the polarization in CIPS changes direction, the graphene/CIPS/graphene ferroelectric diode exhibits switchable resistance since the Fermi level in graphene is modulated by the polarization in CIPS. For CIPS/MoTe2 dual-gate transistor, a temperature-dependent nonvolatile memory window is observed, which can be attributed to the interplay between ferroelectric polarization and interface traps. This research provides experimental groundwork for vdW ferroelectric materials, expands the understanding of ferroelectricity in CIPS, and opens up exciting opportunities for novel electronic devices based on vdW ferroelectric materials.

Ferroelectric Tunneling Junctions Based on Aluminum Oxide/ Zirconium-Doped Hafnium Oxide for Neuromorphic Computing.

Ferroelectric tunneling junctions (FTJs) with tunable tunneling electroresistance (TER) are promising for many emerging applications, including non-volatile memories and neurosynaptic computing. One of the key challenges in FTJs is the balance between the polarization value and the tunneling current. In order to achieve a sizable on-current, the thickness of the ferroelectric layer needs to be scaled down below 5 nm. However, the polarization in these ultra-thin ferroelectric layers is very small, which leads to a low tunneling electroresistance (TER) ratio. In this paper, we propose and demonstrate a new type of FTJ based on metal/Al2O3/Zr-doped HfO2/Si structure. The interfacial Al2O3 layer and silicon substrate enable sizable TERs even when the thickness of Zr-doped HfO2 (HZO) is above 10 nm. We found that F-N tunneling dominates at read voltages and that the polarization switching in HZO can alter the effective tunneling barrier height and tune the tunneling resistance. The FTJ synapses based on Al2O3/HZO stacks show symmetric potentiation/depression characteristics and widely tunable conductance. We also show that spike-timing-dependent plasticity (STDP) can be harnessed from HZO based FTJs. These novel FTJs will have high potential in non-volatile memories and neural network applications.