MoS2 transistors with 1-nanometer gate lengths.

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

Monolithic 3D CMOS Using Layered Semiconductors.

Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications.

Field-effect transistors built from all two-dimensional material components.

We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including the semiconductor, insulator, and metal layers. Specifically, MoS2 is used as the active channel material, hexagonal-BN as the top-gate dielectric, and graphene as the source/drain and the top-gate contacts. This transistor exhibits n-type behavior with an ON/OFF current ratio of >10(6), and an electron mobility of ∼33 cm(2)/V·s. Uniquely, the mobility does not degrade at high gate voltages, presenting an important advantage over conventional Si transistors where enhanced surface roughness scattering severely reduces carrier mobilities at high gate-fields. A WSe2-MoS2 diode with graphene contacts is also demonstrated. The diode exhibits excellent rectification behavior and a low reverse bias current, suggesting high quality interfaces between the stacked layers. In this work, all interfaces are based on van der Waals bonding, presenting a unique device architecture where crystalline, layered materials with atomically uniform thicknesses are stacked on demand, without the lattice parameter constraints. The results demonstrate the promise of using an all-layered material system for future electronic applications.

High-gain inverters based on WSe2 complementary field-effect transistors.

In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is demonstrated. The p-FET is fabricated by contacting WSe2 with a high work function metal, Pt, which facilities hole injection at the source contact. The n-FET is realized by utilizing selective surface charge transfer doping with potassium to form degenerately doped n+ contacts for electron injection. An ON/OFF current ratio of >10(4) is achieved for both n- and p-FETs with similar ON current densities. A dc voltage gain of >12 is measured for the complementary WSe2 inverter. This work presents an important advance toward realization of complementary logic devices based on layered chalcogenide semiconductors for electronic applications.