Dust-Sized High-Power-Density Photovoltaic Cells on Si and SOI Substrates for Wafer-Level-Packaged Small Edge Computers.

Advancement in microelectronics technology enables autonomous edge computing platforms in the size of a dust mote (<1 mm), bringing efficient and low-cost artificial intelligence close to the end user and Internet-of-Things (IoT) applications. The key challenge for these compact high-performance edge computers is the integration of a power source that satisfies the high-power-density requirement and does not increase the complexity and cost of the packaging. Here, it is shown that dust-sized III-V photovoltaic (PV) cells grown on Si and silicon-on-insulator (SOI) substrates can be integrated using a wafer-level-packaging process and achieve higher power density than all prior micro-PVs on Si and SOI substrates. The high-throughput heterogeneous integration unlocks the potential of large-scale manufacturing of these integrated systems with low cost for IoT applications. The negative effect of crystallographic defects in the heteroepitaxial materials on PV performance diminishes at high power density. Simultaneous power delivery and data transmission to the dust mote with heteroepitaxially grown PV are also demonstrated using hand-held illumination sources.

Diffusion-Controlled Porous Crystalline Silicon Lithium Metal Batteries.

Nanostructured porous silicon materials have recently advanced as hosts for Li-metal plating. However, limitations involve detrimental silicon self-pulverization, Li-dendrites, and the ability to achieve wafer-level integration of non-composite, pure silicon anodes. compo. Herein, full cells featuring low-resistance, wafer-scale porous crystalline silicon (PCS) anodes are embedded with a nanoporous Li-plating and diffusion-regulating surface layer upon combined wafer surface cleaning (SC) and anodization. LL Lithiophilic surface formation is illustrated via correlation of surface groups and X-ray structure. Low-cost SC-PCS anodes require no composite formulation, and pre-lithiation enables sustainable Li-metal plating/stripping on the lithiophilic surface and in SC-PCS bulk nanostructure. Anodization time and C-rate determined competitive full cell performance: NMC811 | 4800 s SC-PCS: 195 mAh/g (99.9% coulombic efficiency [C.E.], C/3, 50 cycles), 165 mAh/g, 587 Wh/kg (97.1% C.E., C/3 and C/2 rate, 350 cycles), 24 Ω∗cm2 SC-PCS-resistivity (900 cycles); 160 µm LCO | 500 s SC-PCS: 102 mAh/g (94.1% C.E., 1C, 350 cycles).

Unveiling the carrier transport mechanism in epitaxial graphene for forming wafer-scale, single-domain graphene.

Graphene epitaxy on the Si face of a SiC wafer offers monolayer graphene with unique crystal orientation at the wafer-scale. However, due to carrier scattering near vicinal steps and excess bilayer stripes, the size of electrically uniform domains is limited to the width of the terraces extending up to a few microns. Nevertheless, the origin of carrier scattering at the SiC vicinal steps has not been clarified so far. A layer-resolved graphene transfer (LRGT) technique enables exfoliation of the epitaxial graphene formed on SiC wafers and transfer to flat Si wafers, which prepares crystallographically single-crystalline monolayer graphene. Because the LRGT flattens the deformed graphene at the terrace edges and permits an access to the graphene formed at the side wall of vicinal steps, components that affect the mobility of graphene formed near the vicinal steps of SiC could be individually investigated. Here, we reveal that the graphene formed at the side walls of step edges is pristine, and scattering near the steps is mainly attributed by the deformation of graphene at step edges of vicinalized SiC while partially from stripes of bilayer graphene. This study suggests that the two-step LRGT can prepare electrically single-domain graphene at the wafer-scale by removing the major possible sources of electrical degradation.

Single Crystal Flexible Electronics Enabled by 3D Spalling.

Flexible and stretchable electronics are becoming increasingly important in many emerging applications. Due to the outstanding electrical properties of single crystal semiconductors, there is great interest in releasing single crystal thin films and fabricating flexible electronics with these conventionally rigid materials. In this study the authors report a universal single crystal layer release process, called "3D spalling," extending beyond prior art. In contrast to the conventional way of removing blanket layers from their substrates, the new process reported here enables 3D control over the shape and thickness of the removed regions, allowing direct formation of arbitrarily shaped structures of released film and locally specified thickness for each region. As an exemplary demonstration, silicon flexible tactile sensors are fabricated with sensitivities comparable to those of high performance sensors on rigid substrates. Finite element modeling indicates that the size and thickness of the selectively released features can be tuned over a wide range.

Monolithic III-V on Silicon Plasmonic Nanolaser Structure for Optical Interconnects.

Monolithic integration of III-V semiconductor lasers with Si circuits can reduce cost and enhance performance for optical interconnects dramatically. We propose and investigate plasmonic III-V nanolasers as monolithically integrated light source on Si chips due to many advantages. First, these III-V plasmonic light sources can be directly grown on Si substrates free of crystallographic defects due to the submicron cavity footprint (250 nm × 250 nm) being smaller than the average defect free region size of the heteroepitaxial III-V material on Si. Secondly, the small lateral and vertical dimensions facilitate process co-integration with Si complementary metal-oxide-semiconductor (CMOS) in the front end of the line. Thirdly, combining with monolithically integrated CMOS circuits with low device capacitance and parasitic capacitance, the nano-cavity optoelectronic devices consume orders of magnitude less power than the conventional lasers and reduce the energy consumption. Fourthly, the modulation bandwidth of the plasmonic light-sources is enhanced to significantly higher than conventional lasers due to enhanced photon state density and transition rate. In addition, we show that these device performance are very robust after taking into account the surface recombination and variations in device fabrication processes.

10.5% efficient polymer and amorphous silicon hybrid tandem photovoltaic cell.

Thin-film solar cells made with amorphous silicon (a-Si:H) or organic semiconductors are considered as promising renewable energy sources due to their low manufacturing cost and light weight. However, the efficiency of single-junction a-Si:H or organic solar cells is typically <10%, insufficient for achieving grid parity. Here we demonstrate an efficient double-junction photovoltaic cell by employing an a-Si:H film as a front sub-cell and a low band gap polymer:fullerene blend film as a back cell on planar glass substrates. Monolithic integration of 6.0% efficienct a-Si:H and 7.5% efficient polymer:fullerene blend solar cells results in a power conversion efficiency of 10.5%. Such high-efficiency thin-film tandem cells can be achieved by optical management and interface engineering of fully optimized high-performance front and back cells without sacrificing photovoltaic performance in both cells.

Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene.

There are numerous studies on the growth of planar films on sp(2)-bonded two-dimensional (2D) layered materials. However, it has been challenging to grow single-crystalline films on 2D materials due to the extremely low surface energy. Recently, buffer-assisted growth of crystalline films on 2D layered materials has been introduced, but the crystalline quality is not comparable with the films grown on sp(3)-bonded three-dimensional materials. Here we demonstrate direct van der Waals epitaxy of high-quality single-crystalline GaN films on epitaxial graphene with low defectivity and surface roughness comparable with that grown on conventional SiC or sapphire substrates. The GaN film is released and transferred onto arbitrary substrates. The post-released graphene/SiC substrate is reused for multiple growth and transfer cycles of GaN films. We demonstrate fully functional blue light-emitting diodes (LEDs) by growing LED stacks on reused graphene/SiC substrates followed by transfer onto plastic tapes.

9.4% efficient amorphous silicon solar cell on high aspect-ratio glass microcones.

High aspect-ratio three-dimensional (3D) a-Si:H solar cells have been fabricated to enhance a light absorption path while maintaining a short carrier collection length. Substantial efficiency enhancement in 3D solar cells was achieved due to the boost in JSC with no degradation of FF which is comparable to FF obtained from 2D solar cells.

Layer-resolved graphene transfer via engineered strain layers.

The performance of optimized graphene devices is ultimately determined by the quality of the graphene itself. Graphene grown on copper foils is often wrinkled, and the orientation of the graphene cannot be controlled. Graphene grown on SiC(0001) via the decomposition of the surface has a single orientation, but its thickness cannot be easily limited to one layer. We describe a method in which a graphene film of one or two monolayers grown on SiC is exfoliated via the stress induced with a Ni film and transferred to another substrate. The excess graphene is selectively removed with a second exfoliation process with a Au film, resulting in a monolayer graphene film that is continuous and single-oriented.

Efficient and bright organic light-emitting diodes on single-layer graphene electrodes.

Organic light-emitting diodes are emerging as leading technologies for both high quality display and lighting. However, the transparent conductive electrode used in the current organic light-emitting diode technologies increases the overall cost and has limited bendability for future flexible applications. Here we use single-layer graphene as an alternative flexible transparent conductor, yielding white organic light-emitting diodes with brightness and efficiency sufficient for general lighting. The performance improvement is attributed to the device structure, which allows direct hole injection from the single-layer graphene anode into the light-emitting layers, reducing carrier trapping induced efficiency roll-off. By employing a light out-coupling structure, phosphorescent green organic light-emitting diodes exhibit external quantum efficiency >60%, while phosphorescent white organic light-emitting diodes exhibit external quantum efficiency >45% at 10,000 cd m(-2) with colour rendering index of 85. The power efficiency of white organic light-emitting diodes reaches 80 lm W(-1) at 3,000 cd m(-2), comparable to the most efficient lighting technologies.

Nanoscale chemical templating of Si nanowires seeded with Al.

We describe a new approach for achieving controlled spatial placement of VLS-grown nanowires that uses an oxygen-reactive seed material and an oxygen-containing mask. Oxygen-reactive seed materials are of great interest for electronic applications, yet they cannot be patterned using the approaches developed for noble metal seed materials such as Au. This new process, nanoscale chemical templating, takes advantage of the reactivity of the blanket seed layer by depositing it over a patterned oxide that reacts with the seed material to prevent nanowire growth in undesired locations. Here we demonstrate this technique using Al as the seed material and SiO2 as the mask, and we propose that this methodology will be applicable to other reactive metals that are of interest for nanowire growth. The method has other advantages over conventional patterning approaches for certain applications including reducing patterning steps, flexibility in lithographic techniques, and high growth yields. We demonstrate its application with standard and microsphere lithography. We show a high growth yield and fidelity, with no NWs between openings and a majority of openings occupied by a single vertical nanowire, and discuss the dependence of yield on parameters.

Epitaxial lift-off process for gallium arsenide substrate reuse and flexible electronics.

Epitaxial lift-off process enables the separation of III-V device layers from gallium arsenide substrates and has been extensively explored to avoid the high cost of III-V devices by reusing the substrates. Conventional epitaxial lift-off processes require several post-processing steps to restore the substrate to an epi-ready condition. Here we present an epitaxial lift-off scheme that minimizes the amount of post-etching residues and keeps the surface smooth, leading to direct reuse of the gallium arsenide substrate. The successful direct substrate reuse is confirmed by the performance comparison of solar cells grown on the original and the reused substrates. Following the features of our epitaxial lift-off process, a high-throughput technique called surface tension-assisted epitaxial lift-off was developed. In addition to showing full wafer gallium arsenide thin film transfer onto both rigid and flexible substrates, we also demonstrate devices, including light-emitting diode and metal-oxide-semiconductor capacitor, first built on thin active layers and then transferred to secondary substrates.

Engineering of contact resistance between transparent single-walled carbon nanotube films and a-Si:H single junction solar cells by gold nanodots.

The viability of single-walled carbon nanotubes (SWCNTs) as a transparent conducting electrode on a-Si:H based single junction solar cells was explored. A Schottky barrier formed at a SWCNT/a-Si:H interface was removed by introducing high work function gold nanodots at the SWCNT/a-Si:H interface. This allows comparable device performance from SWCNT-electrode-based a-Si:H solar cells to that obtained by using conventional transparent conducting oxides.

Three-dimensional a-Si:H solar cells on glass nanocone arrays patterned by self-assembled Sn nanospheres.

We introduce a cost-effective method of forming size-tunable arrays of nanocones to act as a three-dimensional (3D) substrate for hydrogenated amorphous silicon (a-Si:H) solar cells. The method is based on self-assembled tin nanospheres with sizes in the range of 20 nm to 1.2 µm. By depositing these spheres on glass substrates and using them as an etch mask, we demonstrate the formation of glass nanopillars or nanocones, depending on process conditions. After deposition of 150 nm thick a-Si:H solar cell p-i-n stacks on the glass nanocones, we show an output efficiency of 7.6% with a record fill factor of ~69% for a nanopillar-based 3D solar cell. This represents up to 40% enhanced efficiency compared to planar solar cells and, to the best of our knowledge, is the first demonstration of nanostructured p-i-n a-Si:H solar cells on glass that is textured without optical lithography patterning methods.

The role of high work-function metallic nanodots on the performance of a-Si:H solar cells: offering ohmic contact to light trapping.

Addition of carbon into p-type "window" layers in hydrogenated amorphous silicon (a-Si:H) solar cells enhances short circuit currents and open circuit voltages by a great deal. However, a-Si:H solar cells with high carbon-doped "window" layers exhibit poor fill factors due to a Schottky barrier-like impedance at the interface between a-SiC:H windows and transparent conducting oxides (TCO), although they show maximized short circuit currents and open circuit voltages. The impedance is caused by an increasing mismatch between the work function of TCO and that of p-type a-SiC:H. Applying ultrathin high-work-function metals at the interface between the two materials results in an effective lowering of the work function mismatch and a consequent ohmic behavior. If the metal layer is sufficiently thin, then it forms nanodots rather than a continuous layer which provides light-scattering effect. We demonstrate 31% efficiency enhancement by using high-work-function materials for engineering the work function at the key interfaces to raise fill factors as well as photocurrents. The use of metallic interface layers in this work is a clear contrast to previous work where attempts were made to enhance the photocurrent using plasmonic metal nanodots on the solar cell surface.