On-site growth of perovskite nanocrystal arrays for integrated nanodevices.

Despite remarkable progress in the development of halide perovskite materials and devices, their integration into nanoscale optoelectronics has been hindered by a lack of control over nanoscale patterning. Owing to their tendency to degrade rapidly, perovskites suffer from chemical incompatibility with conventional lithographic processes. Here, we present an alternative, bottom-up approach for precise and scalable formation of perovskite nanocrystal arrays with deterministic control over size, number, and position. In our approach, localized growth and positioning is guided using topographical templates of controlled surface wettability through which nanoscale forces are engineered to achieve sub-lithographic resolutions. With this technique, we demonstrate deterministic arrays of CsPbBr3 nanocrystals with tunable dimensions down to <50 nm and positional accuracy <50 nm. Versatile, scalable, and compatible with device integration processes, we then use our technique to demonstrate arrays of nanoscale light-emitting diodes, highlighting the new opportunities that this platform offers for perovskites' integration into on-chip nanodevices.

Nanoparticle contact printing with interfacial engineering for deterministic integration into functional structures.

Deterministic, pristine, and scalable integration of individual nanoparticles onto arbitrary surfaces is an ongoing challenge, yet essential for harnessing their unique properties for functional nanoscale devices. To address this challenge, we present a versatile technique where spatially arranged nanoparticles assembled in a topographical template are printed onto diverse surfaces, through a single contact-and-release step, with >95% transfer yield and <50-nanometer placement accuracy. Through engineering of interfacial interactions, our approach uniquely promotes high-yield transfer of individual particles without needing solvents, surface treatments, and polymer sacrificial layers, which are conventionally inevitable. By avoiding these mediation steps, surfaces can remain damage and contamination free and accessible to integrate into functional structures. We demonstrate this in a particle-on-mirror model system, where >2000 precisely defined nanocavities display a consistent plasmonic response with minimized interstructure variability. Through fabricating arrays of emitter-coupled nanocavities, we further highlight the integration opportunities offered by our contact printing.

Significant Phonon Drag Enables High Power Factor in the AlGaN/GaN Two-Dimensional Electron Gas.

In typical thermoelectric energy harvesters and sensors, the Seebeck effect is caused by diffusion of electrons or holes in a temperature gradient. However, the Seebeck effect can also have a phonon drag component, due to momentum exchange between charge carriers and lattice phonons, which is more difficult to quantify. Here, we present the first study of phonon drag in the AlGaN/GaN two-dimensional electron gas (2DEG). We find that phonon drag does not contribute significantly to the thermoelectric behavior of devices with ∼100 nm GaN thickness, which suppresses the phonon mean free path. However, when the thickness is increased to ∼1.2 µm, up to 32% (88%) of the Seebeck coefficient at 300 K (50 K) can be attributed to the drag component. In turn, the phonon drag enables state-of-the-art thermoelectric power factor in the thicker GaN film, up to ∼40 mW m-1 K-2 at 50 K. By measuring the thermal conductivity of these AlGaN/GaN films, we show that the magnitude of the phonon drag can increase even when the thermal conductivity decreases. Decoupling of thermal conductivity and Seebeck coefficient could enable important advancements in thermoelectric power conversion with devices based on 2DEGs.

Engineering Interfacial Silicon Dioxide for Improved Metal-Insulator-Semiconductor Silicon Photoanode Water Splitting Performance.

Silicon photoanodes protected by atomic layer deposited (ALD) TiO2 show promise as components of water splitting devices that may enable the large-scale production of solar fuels and chemicals. Minimizing the resistance of the oxide corrosion protection layer is essential for fabricating efficient devices with good fill factor. Recent literature reports have shown that the interfacial SiO2 layer, interposed between the protective ALD-TiO2 and the Si anode, acts as a tunnel oxide that limits hole conduction from the photoabsorbing substrate to the surface oxygen evolution catalyst. Herein, we report a significant reduction of bilayer resistance, achieved by forming stable, ultrathin (<1.3 nm) SiO2 layers, allowing fabrication of water splitting photoanodes with hole conductances near the maximum achievable with the given catalyst and Si substrate. Three methods for controlling the SiO2 interlayer thickness on the Si(100) surface for ALD-TiO2 protected anodes were employed: (1) TiO2 deposition directly on an HF-etched Si(100) surface, (2) TiO2 deposition after SiO2 atomic layer deposition on an HF-etched Si(100) surface, and (3) oxygen scavenging, post-TiO2 deposition to decompose the SiO2 layer using a Ti overlayer. Each of these methods provides a progressively superior means of reliably thinning the interfacial SiO2 layer, enabling the fabrication of efficient and stable water oxidation silicon anodes.