Highly reproducible surface-enhanced Raman scattering substrate for detection of phenolic pollutants.

The ordering degree of nanostructures is the key to determining the uniformity of surface-enhanced Raman scattering (SERS). However, fabrication of large-area ordered nanostructures remains a challenge, especially with the ultrahigh-density (>1010 cm-2). Here, we report a fabrication of large-area ultrahigh-density ordered Ag@Al2O3/Ag core-shell nanosphere (NS) arrays with tunable nanostructures. The ultrahigh-density (2.8 × 1010 cm-2) ordered NS arrays over a large-area capability (diameter >4.0 cm) enable the uniform SERS signals with the relative standard deviation of less than 5%. The as-fabricated highly reproducible SERS substrate can be applied to detect trace phenolic pollutants in water. This work does not only provide a new route for synthesizing the ultrahigh-density ordered nanostructures, but also create a new class of SERS substrates with high sensitivity and excellent reproducibility.

Epitaxial growth of vertically free-standing ultra-thin silicon nanowires.

We report epitaxial growth of ultra-thin vertically free-standing silicon nanowires (Si NWs) on Si(111) and Si(110) substrate, by an ultra-high vacuum chemical vapor deposition method. The epitaxial growth direction of Si NWs with sub-10 nm diameters was found to be dependent upon the orientation type of the Si substrate. The 〈112〉 and 〈110〉 epitaxial growth directions are crystallographically preferred on Si(111) and Si(110) substrates, respectively. Especially, for the epitaxy on Si(110), most of the Si NWs are grown vertically in the [110] direction with sub-5 nm diameters. Based on transmission electron microscope investigations, a growth model for ultra-thin Si NWs was deduced from the morphology of interface between catalyst and nanowire, and the growth direction at a very early stage of epitaxy was determined.

Colossal injection of catalyst atoms into silicon nanowires.

The incorporation of impurities during the growth of nanowires from the vapour phase alters their basic properties substantially, and this process is critical in an extended range of emerging nanometre-scale technologies. In particular, achieving precise control of the behaviour of group III and group V dopants has been a crucial step in the development of silicon (Si) nanowire-based devices. Recently it has been demonstrated that the use of aluminium (Al) as a growth catalyst, instead of the usual gold, also yields an effective p-type doping, thereby enabling a novel and efficient route to functionalizing Si nanowires. Besides the technological implications, this self-doping implies the detachment of Al from the catalyst and its injection into the growing nanowire, involving atomic-scale processes that are crucial for the fundamental understanding of the catalytic assembly of nanowires. Here we present an atomic-level, quantitative study of this phenomenon of catalyst dissolution by three-dimensional atom-by-atom mapping of individual Al-catalysed Si nanowires using highly focused ultraviolet-laser-assisted atom-probe tomography. Although the observed incorporation of the catalyst atoms into nanowires exceeds by orders of magnitude the equilibrium solid solubility and solid-solution concentrations in known non-equilibrium processes, the Al impurities are found to be homogeneously distributed in the nanowire and do not form precipitates or clusters. As well as the anticipated effect on the electrical properties, this kinetics-driven colossal injection also has direct implications for nanowire morphology. We discuss the observed strong deviation from equilibrium using a model of solute trapping at step edges, and identify the key growth parameters behind this phenomenon on the basis of a kinetic model of step-flow growth of nanowires. The control of this phenomenon provides opportunities to create a new class of nanoscale devices by precisely tailoring the shape and composition of metal-catalysed nanowires.

Atomically smooth p-doped silicon nanowires catalyzed by aluminum at low temperature.

Silicon nanowires (SiNWs) are powerful nanotechnological building blocks. To date, a variety of metals have been used to synthesize high-density epitaxial SiNWs through metal-catalyzed vapor phase epitaxy. Understanding the impact of the catalyst on the intrinsic properties of SiNWs is critical for precise manipulation of the emerging SiNW-based devices. Here we demonstrate that SiNWs synthesized at low-temperature by ultrahigh vacuum chemical vapor deposition using Al as a catalyst present distinct morphological properties. In particular, these nanowires are atomically smooth in contrast to rough {112}-type sidewalls characteristic of the intensively investigated Au-catalyzed SiNWs. We show that the stabilizing effect of Al plays the key role in the observed nanowire surface morphology. In fact, unlike Au which induces (111) and (113) facets on the nanowire sidewall surface, Al revokes the reconstruction along the [112] direction leading to equivalent adjacent step edges and flat surfaces. Our finding sets the lower limit of the Al surface density on the nanowire sidewalls at ∼2 atom/nm(2). Additionally, despite using temperatures of ca. 110-170 K below the eutectic point, we found that the incorporation of Al into the growing nanowires is sufficient to induce an effective p-type doping of SiNWs. These results demonstrate that the catalyst plays a crucial role is shaping the structural and electrical properties of SiNWs.

Synthesis of silicon nanotubes with cobalt silicide ends using anodized aluminum oxide template.

Silicon nanotubes (SiNTs) are compatible with Si-based semiconductor technology. In particular, the small diameters and controllable structure of such nanotubes are remaining challenges. Here we describe a method to fabricate SiNTs intrinsically connected with cobalt silicide ends based on highly ordered anodic aluminum oxide (AAO) templates. Size and growth direction of the SiNTs can be well controlled via the templates. The growth of SiNTs is catalyzed by the Co nanoparticles reduced on the pore walls of the AAO after annealing, with a controllable thickness at a given growth temperature and time. Simultaneously, cobalt silicide forms on the bottom side of the SiNTs.

Ordered arrays of vertically aligned [110] silicon nanowires by suppressing the crystallographically preferred <100> etching directions.

The metal-assisted etching direction of Si(110) substrates was found to be dependent upon the morphology of the deposited metal catalyst. The etching direction of a Si(110) substrate was found to be one of the two crystallographically preferred 100 directions in the case of isolated metal particles or a small area metal mesh with nanoholes. In contrast, the etching proceeded in the vertical [110] direction, when the lateral size of the catalytic metal mesh was sufficiently large. Therefore, the direction of etching and the resulting nanostructures obtained by metal-assisted etching can be easily controlled by an appropriate choice of the morphology of the deposited metal catalyst. On the basis of this finding, a generic method was developed for the fabrication of wafer-scale vertically aligned arrays of epitaxial [110] Si nanowires on a Si(110) substrate. The method utilized a thin metal film with an extended array of pores as an etching catalyst based on an ultrathin porous anodic alumina mask, while a prepatterning of the substrate prior to the metal depostion is not necessary. The diameter of Si nanowires can be easily controlled by a combination of the pore diameter of the porous alumina film and varying the thickness of the deposited metal film.

Vertical epitaxial wire-on-wire growth of Ge/Si on Si(100) substrate.

Vertically aligned epitaxial Ge/Si heterostructure nanowire arrays on Si(100) substrates were prepared by a two-step chemical vapor deposition method in anodic aluminum oxide templates. n-Butylgermane vapor was employed as new safer precursor for Ge nanowire growth instead of germane. First a Si nanowire was grown by the vapor liquid solid growth mechanism using Au as catalyst and silane. The second step was the growth of Ge nanowires on top of the Si nanowires. The method presented will allow preparing epitaxially grown vertical heterostructure nanowires consisting of multiple materials on an arbitrary substrate avoiding undesired lateral growth.

Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties.

This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor-liquid-solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs-Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

Extended arrays of vertically aligned sub-10 nm diameter [100] Si nanowires by metal-assisted chemical etching.

Large-area high density silicon nanowire (SiNW) arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic film on a Si (100) substrate. Both the diameter of the pores in the AAO mask and the thickness of the metal film affected the diameter of SiNWs. The diameter of the SiNWs decreased with an increase of thickness of the metal film. Large-area SiNWs with average diameters of 20 nm down to 8 nm and wire densities as high as 10 (10) wires/cm (2) were accomplished. These SiNWs were single crystalline and vertically aligned to the (100) substrate. It was revealed by transmission electron microscopy that the SiNWs were of high crystalline quality and showed a smooth surface.

Individually addressable epitaxial ferroelectric nanocapacitor arrays with near Tb inch-2 density.

Ferroelectric materials have emerged in recent years as an alternative to magnetic and dielectric materials for nonvolatile data-storage applications. Lithography is widely used to reduce the size of data-storage elements in ultrahigh-density memory devices. However, ferroelectric materials tend to be oxides with complex structures that are easily damaged by existing lithographic techniques, so an alternative approach is needed to fabricate ultrahigh-density ferroelectric memories. Here we report a high-temperature deposition process that can fabricate arrays of individually addressable metal/ferroelectric/metal nanocapacitors with a density of 176 Gb inch(-2). The use of an ultrathin anodic alumina membrane as a lift-off mask makes it possible to deposit the memory elements at temperatures as high as 650 degrees C, which results in excellent ferroelectric properties.

Measurement of the bending strength of vapor-liquid-solid grown silicon nanowires.

The fracture strength of silicon nanowires grown on a [111] silicon substrate by the vapor-liquid-solid process was measured. The nanowires, with diameters between 100 and 200 nm and a typical length of 2 microm, were subjected to bending tests using an atomic force microscopy setup inside a scanning electron microscope. The average strength calculated from the maximum nanowire deflection before fracture was around 12 GPa, which is 6% of the Young's modulus of silicon along the nanowire direction. This value is close to the theoretical fracture strength, which indicates that surface or volume defects, if present, play only a minor role in fracture initiation.

Epitaxial growth of silicon nanowires using an aluminium catalyst.

Silicon nanowires have been identified as important components for future electronic and sensor nanodevices. So far gold has dominated as the catalyst for growing Si nanowires via the vapour-liquid-solid (VLS) mechanism. Unfortunately, gold traps electrons and holes in Si and poses a serious contamination problem for Si complementary metal oxide semiconductor (CMOS) processing. Although there are some reports on the use of non-gold catalysts for Si nanowire growth, either the growth requires high temperatures and/or the catalysts are not compatible with CMOS requirements. From a technological standpoint, a much more attractive catalyst material would be aluminium, as it is a standard metal in Si process lines. Here we report for the first time the epitaxial growth of Al-catalysed Si nanowires and suggest that growth proceeds via a vapour-solid-solid (VSS) rather than a VLS mechanism. It is also found that the tapering of the nanowires can be strongly reduced by lowering the growth temperature.

Diameter-dependent growth direction of epitaxial silicon nanowires.

We found that silicon nanowires grown epitaxially on Si (100) via the vapor-liquid-solid growth mechanism change their growth direction from 111 to 110 at a crossover diameter of approximately 20 nm. A model is proposed for the explanation of this phenomenon. We suggest that the interplay of the liquid-solid interfacial energy with the silicon surface energy expressed in terms of an edge tension is responsible for the change of the growth direction. The value of the edge tension is estimated by the product of the interfacial thickness with the surface energy of silicon. For large diameters, the direction with the lowest interfacial energy is dominant, whereas for small diameters the surface energy of the silicon nanowire determines the preferential growth direction.