Design, implementation, and characterization of a kinematically aligned, cascaded spot- array generator for a modulator-based free-space optical interconnect.

The design and the implementation of a modular spot-array generator for a modulator-based free-space optical interconnect is presented. Two cascaded diffractive optical elements produce 4 x 8 clusters on a 1600 microm x 800 microm pitch, where each cluster is a 4 x 4 array of (1/e(2)) 13.1-microm-radius spots on a 90-microm pitch. The spot-array generator is kinematically aligned to the interconnect system such that no realignment is necessary between removal and reinsertion. Characterization results are presented.

Optical design of a 1024-channel free-space sorting demonstrator.

We describe the optical design of a free-space interconnect system to be used for a 32 x 32 sorting system. The system uses 4f imaging relays to connect two hybrid optoelectronic-complementary metal-oxide semiconductor chips. These relays are used to implement a perfect-shuffle interconnect necessary for the sorting algorithm to be implemented. The relay lenses are also used with patterned mirrors and polarizing elements to combine read beams necessary for the optoelectronic chips. Issues relating to the basic system design and the detailed design of the lenses and optomechanics are given.

Optical lateral inhibition networks that use self-linearized self-electro-optic-effect devices: theory and experiment.

The self-linearized self-electro-optic-effect-device (SL-SEED) phenomenon observed with a quantum-well modulator and photodiode serial combination is one of the few practical routes to optical subtraction. A family of optical lateral inhibition architectures based on the SL-SEED that incorporate optical feedback is introduced and their operation confirmed in simulation. A successful experimental demonstration based on these ideas, performing edge-contrast enhancement by lateral inhibition, is described. System interconnections are both optical and electrical, with nonlocal interconnections being made optically by the use of diffractive elements.

Implementation of optical perfect-shuffle module.

Experimental details are presented of the measured performance of a novel implementation of a cascadable module for the one-dimensional perfect shuffle of a two-dimensional array of optical signals. The design uses an anamorphic telescope to correct the difference in pitch in the two axes resulting from an image split and recombine operation performed with patterned mirrors. The performance of the cylindrical lens limits the scalability of the design.

Perfect-shuffle interconnected bitonic sorter: optoelectronic design.

The algorithmic, electronic, and optical aspects of the implementation of a perfect-shuffle interconnected bitonic sorter are analyzed. The performance metrics such as the bit output data rate and the power consumption of the system are quantified. The sorting module is designed to demonstrate the parallel nonlocal interconnection of smart-pixel arrays and the use of optical-image control masks in a functioning information processor.

Implementation of a hybrid lens.

Details are presented of the design, fabrication, and use of a hybrid lens employed to interconnect two-dimensional arrays of optical transceivers. The hybrid lens consists of a custom-designed, 42-mm focal length, ƒ/5 compound lens followed by an array of afocal telescope compound microlenses.

Optical computing: introduction by the feature editors.

This feature of Applied Optics: Information Processing on optical computing comprises thirty papers. Most of the papers evolved from papers presented at the Fifth Topical Meeting on Optical Computing held in March 1993 in Palm Springs, California.

Relationships between speed and tolerances for self-electro-optic-effect devices.

We describe a method of calculating the relationship between system bit rates and tolerances to variations in optical powers for self-electro-optic-effect devices (SEED's). We show that high-contrast-ratio devices have improved bit rates in the presence of optical-power variations even for differential devices. We also calculate the ratios of control-beam to signal-beam powers and transfer-beam to clock-beam powers for logic SEED switching nodes and shift registers. Last, we show that the bit rate of optoelectronically cascaded devices, such as the logic SEED shift register, is comparable with that of optically cascaded symmetric SEED's.

Interconnects for a symmetric-self-electro-optic-effect-device cellular-logic image processor.

An optical circuit is successfully operated by interconnecting two arrays of 128 symmetric self-electro-opticeffect devices. The holographic interconnect used in this cellular-logic image processor is described. The design issues (noise orders, efficiency, and ease of alignment) associated with the interconnect and and extensions of it are discussed.

Design of a symmetric self-electro-optic-effect-device cellular-logic image processor.

A cellular-logic image processor was designed, constructed, and successfully operated by interconnecting two arrays of 128 symmetric self-electro-optic-effect devices. Design issues associated with the implementation of this free-space digital-optical system are discussed.

Six-stage digital free-space optical switching network using symmetric self-electro-optic-effect devices.

We describe the design and demonstration of an extended generalized shuffle interconnection network, centrally controlled by a personal computer. A banyan interconnection pattern is implemented by use of computer-generated Fourier holograms and custom metallization at each 32 × 32 switching node array. Each array of electrically controlled tristate symmetric self-electro-optic-effect devices has 10,240 optical pinouts and 32 electrical pinouts, and the six-stage system occupies a 9 in. × 12.5 in. (22.9 cm × 31.7 cm) area. Details of the architecture, optical and mechanical design, and system alignment and tolerancing are presented.

Experimental investigation of a free-space optical switching network by using symmetric self-electro-optic-effect devices.

A prototype digital free-space photonic switching fabric is demonstrated. It consists of three cascaded 16 x 8 arrays of symmetric self-electro-optic-effect devices that are used as logic gates that implement part of a multistage interconnection network. We discuss architecture, device tolerancing, optical system design, and optomechanical design. This optical circuit is successfully configured as a fully operational array of 32 independent 2 x 2 nodes and operates at 100 kHz.

Optical cellular logic image processor: implementation and programming of a single channel digital optical circuit.

A diode-laser driven all-optical iterative processor has been constructed and tested. Results are presented showing operation equivalent to a single channel of the cellular logic image processor architecture. Functional features of the circuit include optically programmable logic, thresholding, and data synchronization. Essential elements such as cascadability, logic-level restoration, and data feedback have been demonstrated with the optical processor controlled by a conventional electronic computer. Serial processing algorithms for word recognition, comparison, full addition, and subtraction have been implemented. Comments on the reliability of operation and future plans for expansion are made.

All-optical programmable logic gate.

Experimental results are presented showing all-optical programmability and operation of a multifunction Boolean logic gate. All eight symmetric two-input logic functions have been demonstrated. Comments on the practical implementation and usage of this gate within an optical circuit are made.

Unidirectional operation of a ring laser using an absorbing Fabry-Perot filter.

We propose a new method for obtaining unidirectional operation of a ring laser using the asymmetric properties of an absorbing Fabry-Perot étalon.

Fan-out considerations of digital optical circuits.

The use of intrinsic optically bistable devices in the construction of all-optical digital circuits is discussed. Analysis of a novel experimental technique is presented which partly alleviates the problems of critical slowing down and low fan-out capability for etalon devices.