Differential pressure sensors based on transfer-free piezoresistive layered PdSe2thin films.

Piezoresistive layered two-dimensional (2D) crystals offer intriguing promise as pressure sensors for microelectromechanical systems (MEMS) due to their remarkable strain-induced conductivity modulation. However, integration of the conventional chemical vapor deposition grown 2D thin films onto a micromachined silicon platform requires a complex transfer process, which degrades their strain-sensing performance. In this study, we present a differential pressure sensor built on a transfer-free piezoresistive PdSe2polycrystalline film deposited on a SiNxmembrane by plasma-enhanced selenization of a metal film at a temperature as low as 200 °C. Based on the resistance change and finite element strain analysis of the film under membrane deflection, we show that a 7.9 nm thick PdSe2film has a gauge factor (GF) of -43.3, which is ten times larger than that of polycrystalline silicon. The large GF enables the development of a diaphragm pressure sensor with a high sensitivity of 3.9 × 10-4kPa-1within the differential pressure range of 0-60 kPa. In addition, the sensor with a Wheatstone bridge circuit achieves a high voltage sensitivity of 1.04 mV·kPa-1, a rapid response time of less than 97 ms, and small output voltage variation of 8.1 mV in the temperature range of 25 °C to 55 °C. This transfer-free and low-temperature grown PdSe2piezoresistive thin film is promising for MEMS transducer devices.

Genetic algorithm-based optical proximity correction for DMD maskless lithography.

We present an optical proximity correction (OPC) method based on a genetic algorithm for reducing the optical proximity effect-induced pattern distortion in digital micromirror device (DMD) maskless lithography. Via this algorithm-assisted grayscale modulation of the initial mask at the pixel level, the exposure pattern can be enhanced significantly. Actual exposure experiments revealed that the rate of matching between the final exposure pattern and the mask pattern can be increased by up to 20%. This method's applicability to complex masks further demonstrates its universality for mask pattern optimization. We believe that our algorithm-assisted OPC could be highly helpful for high-fidelity and efficient DMD maskless lithography for microfabrication.

Thickness-dependent carrier transport of PdSe2films grown by plasma-assisted metal selenization.

Atomically thin narrow-bandgap layered PdSe2has attracted much attention due to its rich and unique electrical properties. For silicon-compatible device integration, direct wafer-scale preparation of high-quality PdSe2thin film on a silicon substrate is highly desired. Here, we present the low-temperature synthesis of large-area polycrystalline PdSe2films grown on SiO2/Si substrates by plasma-assisted metal selenization and investigate their charge carrier transport behaviors. Raman analysis, depth-dependent x-ray photoelectron spectroscopy, and cross-sectional transmission electron microscopy were used to reveal the selenization process. The results indicate a structural evolution from initial Pd to intermediate PdSe2-xphase and eventually to PdSe2. The field-effect transistors fabricated from these ultrathin PdSe2films exhibit strong thickness-dependent transport behaviors. For thinner films (4.5 nm), a record high on/off ratio of 104was obtained. While for thick ones (11 nm), the maximum hole mobility is about 0.93 cm2V-1S-1, which is the record high value ever reported for polycrystalline films. These findings suggest that our low-temperature-metal-selenized PdSe2films have high quality and show great potential for applications in electrical devices.

Gate-bias instability of few-layer WSe2 field effect transistors.

Semiconducting two-dimensional (2D) layered materials have shown great potential in next-generation electronics due to their novel electronic properties. However, the performance of field effect transistors (FETs) based on 2D materials is always environment-dependent and unstable under gate bias stress. Here, we report the environment-dependent performance and gate-induced instability of few-layer p-type WSe2-based FETs. We found that the hole mobility of the transistor drastically reduces in vacuum and further decreases after in situ annealing in vacuum compared with that in air, which can be recovered after exposure to air. The on-current of the WSe2 FET increases with positive gate bias stress time but decreases with negative gate bias stress time. For the double sweeping transfer curve, the transistor shows prominent hysteresis, which depends on both the sweeping rate and the sweeping range. Large hysteresis can be observed when a slow sweeping rate or large sweeping range is applied. In addition, such gate-induced instability can be reduced in vacuum and further reduced after in situ vacuum annealing. However, the gate-induced instability cannot be fully eliminated, which suggests both gases adsorbed on the device and defects in the WSe2 channel and/or the interface of WSe2/SiO2 are responsible for the gate-induced instability. Our results provide a deep understanding of the gate-induced instability in p-type WSe2 based transistors, which may shed light on the design of high-performance 2D material-based electronics.