Dimensional Scaling of Ferroelectric Properties of Hafnia-Zirconia Thin Films: Electrode Interface Effects.

Hafnia-based ferroelectric (FE) thin films are promising candidates for semiconductor memories. However, a fundamental challenge that persists is the lack of understanding regarding dimensional scaling, including thickness scaling and area scaling, of the functional properties and their heterogeneity in these films. In this work, excellent ferroelectricity and switching endurance are demonstrated in 4 nm-thick Hf0.5Zr0.5O2 (HZO) capacitors with molybdenum electrodes in capacitors as small as 65 nm × 45 nm in size. The HZO layer in these capacitors can be crystallized into the ferroelectric orthorhombic phase at the low temperature of 400 °C, making them compatible for back-end-of-line (BEOL) FE memories. With the benefits of thickness scaling, low operation voltage (1.2 V) is achieved with high endurance (>1010 cycles); however, a significant fatigue regime is noted. We observed that the bottom electrode, rather than the top electrode, plays a dominant role in the thickness scaling of HZO ferroelectric behavior. Furthermore, ultrahigh switched polarization (remanent polarization 2Pr ∼ 108 µC cm-2) is observed in some nanoscale devices. This study advances the understanding of dimensional scaling effects in HZO capacitors for high-performance FE memories.

Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory.

Data-centric applications are pushing the limits of energy-efficiency in today's computing systems, including those based on phase-change memory (PCM). This technology must achieve low-power and stable operation at nanoscale dimensions to succeed in high-density memory arrays. Here we use a novel combination of phase-change material superlattices and nanocomposites (based on Ge4Sb6Te7), to achieve record-low power density ≈ 5 MW/cm2 and ≈ 0.7 V switching voltage (compatible with modern logic processors) in PCM devices with the smallest dimensions to date (≈ 40 nm) for a superlattice technology on a CMOS-compatible substrate. These devices also simultaneously exhibit low resistance drift with 8 resistance states, good endurance (≈ 2 × 108 cycles), and fast switching (≈ 40 ns). The efficient switching is enabled by strong heat confinement within the superlattice materials and the nanoscale device dimensions. The microstructural properties of the Ge4Sb6Te7 nanocomposite and its high crystallization temperature ensure the fast-switching speed and stability in our superlattice PCM devices. These results re-establish PCM technology as one of the frontrunners for energy-efficient data storage and computing.

Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors.

Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current (IMIN) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of IMIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.

Area-Selective Atomic Layer Deposition for Resistive Random-Access Memory Devices.

Resistive random-access memory (RRAM) is a promising technology for data storage and neuromorphic computing; however, cycle-to-cycle and device-to-device variability limits its widespread adoption and high-volume manufacturability. Improving the structural accuracy of RRAM devices during fabrication can reduce these variabilities by minimizing the filamentary randomness within a device. Here, we studied area-selective atomic layer deposition (AS-ALD) of the HfO2 dielectric for the fabrication of RRAM devices with higher reliability and accuracy. Without requiring photolithography, first we demonstrated ALD of HfO2 patterns uniformly and selectively on Pt bottom electrodes for RRAM but not on the underlying SiO2/Si substrate. RRAM devices fabricated using AS-ALD showed significantly narrower operating voltage range (2.6 × improvement) and resistance states than control devices without AS-ALD, improving the overall reliability of RRAM. Irrespective of device size (1 × 1, 2 × 2, and 5 × 5 µm2), we observed similar improvement, which is an inherent outcome of the AS-ALD technique. Our demonstration of AS-ALD for improved RRAM devices could further encourage the adoption of such techniques for other data storage technologies, including phase-change, magnetic, and ferroelectric RAM.

Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems.

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Probing the Melting Transitions in Phase-Change Superlattices via Thin Film Nanocalorimetry.

Phase-change superlattices with nanometer thin sublayers are promising for low-power phase-change memory (PCM) on rigid and flexible platforms. However, the thermodynamics of the phase transition in such nanoscale superlattices remain unexplored, especially at ultrafast scanning rates, which is crucial for our fundamental understanding of superlattice-based PCM. Here, we probe the phase transition of Sb2Te3 (ST)/Ge2Sb2Te5 (GST) superlattices using nanocalorimetry with a monolayer sensitivity (∼1 Å) and a fast scanning rate (105 K/s). For a 2/1.8 nm/nm Sb2Te3/GST superlattice, we observe an endothermic melting transition with an ∼240 °C decrease in temperature and an ∼8-fold decrease in enthalpy compared to those for the melting of GST, providing key thermodynamic insights into the low-power switching of superlattice-based PCM. Nanocalorimetry measurements for Sb2Te3 alone demonstrate an intrinsic premelting similar to the unique phase transition of superlattices, thus revealing a critical role of the Sb2Te3 sublayer within our superlattices. These results advance our understanding of superlattices for energy-efficient data storage and computing.

Carbon nanotube transistors: Making electronics from molecules.

Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementation to devices that work in conjunction with silicon electronics, and can potentially be used as a platform for high-performance digital electronics as well as radio-frequency and sensing applications. Recent progress in the materials, devices, and technologies related to carbon nanotube transistors is briefly reviewed. Emphasis is placed on the most broadly impactful advancements that have evolved from single-nanotube devices to implementations with aligned nanotubes and even nanotube thin films. There are obstacles that remain to be addressed, including material synthesis and processing control, device structure design and transport considerations, and further integration demonstrations with improved reproducibility and reliability; however, the integration of more than 10,000 devices in single functional chips has already been realized.

Nanocrystallite Seeding of Metastable Ferroelectric Phase Formation in Atomic Layer-Deposited Hafnia-Zirconia Alloys.

Hafnia-based ferroelectric thin films are promising for semiconductor memory and neuromorphic computing applications. Amorphous, as-deposited, thin-film binary alloys of HfO2 and ZrO2 transform to the metastable, orthorhombic ferroelectric phase during post-deposition annealing and cooling. This transformation is generally thought to involve formation of a tetragonal precursor phase that distorts into the orthorhombic phase during cooling. In this work, we systematically study the effects of atomic layer deposition (ALD) temperature on the ferroelectricity of post-deposition-annealed Hf0.5Zr0.5O2 (HZO) thin films. Seed crystallites having interplanar spacings consistent with the polar orthorhombic phase are observed by a plan-view transmission electron microscope in HZO thin films deposited at an elevated ALD temperature. After ALD under conditions that promote formation of these nanocrystallites, high-polarization (Pr > 18 µC/cm2) ferroelectric switching is observed after rapid thermal annealing (RTA) at low temperature (350 °C). These results indicate the presence of minimal non-ferroelectric phases retained in the films after RTA when the ALD process forms nanocrystalline particles that seed subsequent formation of the polar orthorhombic phase.

Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2.

Scaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS2 FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.

A compute-in-memory chip based on resistive random-access memory.

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance.

Superlattice (SL) phase change materials have shown promise to reduce the switching current and resistance drift of phase change memory (PCM). However, the effects of internal SL interfaces and intermixing on PCM performance remain unexplored, although these are essential to understand and ensure reliable memory operation. Here, using nanometer-thin layers of Ge2Sb2Te5 and Sb2Te3 in SL-PCM, we uncover that both switching current density (Jreset) and resistance drift coefficient (v) decrease as the SL period thickness is reduced (i.e., higher interface density); however, interface intermixing within the SL increases both. The signatures of distinct versus intermixed interfaces also show up in transmission electron microscopy, X-ray diffraction, and thermal conductivity measurements of our SL films. Combining the lessons learned, we simultaneously achieve low Jreset ≈ 3-4 MA/cm2 and ultralow v ≈ 0.002 in mushroom-cell SL-PCM with ∼110 nm bottom contact diameter, thus advancing SL-PCM technology for high-density storage and neuromorphic applications.

Ultralow-switching current density multilevel phase-change memory on a flexible substrate.

Phase-change memory (PCM) is a promising candidate for data storage in flexible electronics, but its high switching current and power are often drawbacks. In this study, we demonstrate a switching current density of ~0.1 mega-ampere per square centimeter in flexible superlattice PCM, a value that is one to two orders of magnitude lower than in conventional PCM on flexible or silicon substrates. This reduced switching current density is enabled by heat confinement in the superlattice material, assisted by current confinement in a pore-type device and the thermally insulating flexible substrate. Our devices also show multilevel operation with low resistance drift. The low switching current and good resistance on/off ratio are retained before, during, and after repeated bending and cycling. These results pave the way to low-power memory for flexible electronics and also provide key insights for PCM optimization on conventional silicon substrates.

Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2.

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS2 films at 560 °C in 50 min, within the 450-to-600 °C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ∼140 µA/µm at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS2 grown below 600 °C using solid-source precursors. The effective mobility from transfer length method test structures is 29 ± 5 cm2 V-1 s-1 at 6.1 × 1012 cm-2 electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

Ultrathin Three-Monolayer Tunneling Memory Selectors.

High-density memory arrays require selector devices, which enable selection of a specific memory cell within a memory array by suppressing leakage current through unselected cells. Such selector devices must have highly nonlinear current-voltage characteristics and excellent endurance; thus selectors based on a tunneling mechanism present advantages over those based on the physical motion of atoms or ions. Here, we use two-dimensional (2D) materials to build an ultrathin (three-monolayer-thick) tunneling-based memory selector. Using a sandwich of h-BN, MoS2, and h-BN monolayers leads to an "H-shaped" energy barrier in the middle of the heterojunction, which nonlinearly modulates the tunneling current when the external voltage is varied. We experimentally demonstrate that tuning the MoS2 Fermi level can improve the device nonlinearity from 10 to 25. These results provide a fundamental understanding of the tunneling process through atomically thin 2D heterojunctions and lay the foundation for developing high endurance selectors with 2D heterojunctions, potentially enabling high-density non-volatile memory systems.

Electrical tuning of phase-change antennas and metasurfaces.

The success of semiconductor electronics is built on the creation of compact, low-power switching elements that offer routing, logic and memory functions. The availability of nanoscale optical switches could have a similarly transformative impact on the development of dynamic and programmable metasurfaces, optical neural networks and quantum information processing. Phase-change materials are uniquely suited to enable their creation as they offer high-speed electrical switching between amorphous and crystalline states with notably different optical properties. Their high refractive index has already been harnessed to fashion them into compact optical antennas. Here, we take the next important step, by showing electrically-switchable phase-change antennas and metasurfaces that offer strong, reversible, non-volatile, multi-phase switching and spectral tuning of light scattering in the visible and near-infrared spectral ranges. Their successful implementation relies on a careful joint thermal and optical optimization of the antenna elements that comprise a silver strip that simultaneously serves as a plasmonic resonator and a miniature heating stage. Our metasurface affords electrical modulation of the reflectance by more than fourfold at 755 nm.

Intracellular detection and communication of a wireless chip in cell.

The rapid growth and development of technology has had significant implications for healthcare, personalized medicine, and our understanding of biology. In this work, we leverage the miniaturization of electronics to realize the first demonstration of wireless detection and communication of an electronic device inside a cell. This is a significant forward step towards a vision of non-invasive, intracellular wireless platforms for single-cell analyses. We demonstrate that a 25 [Formula: see text]m wireless radio frequency identification (RFID) device can not only be taken up by a mammalian cell but can also be detected and specifically identified externally while located intracellularly. The S-parameters and power delivery efficiency of the electronic communication system is quantified before and after immersion in a biological environment; the results show distinct electrical responses for different RFID tags, allowing for classification of cells by examining the electrical output noninvasively. This versatile platform can be adapted for realization of a broad modality of sensors and actuators. This work precedes and facilitates the development of long-term intracellular real-time measurement systems for personalized medicine and furthering our understanding of intrinsic biological behaviors. It helps provide an advanced technique to better assess the long-term evolution of cellular physiology as a result of drug and disease stimuli in a way that is not feasible using current methods.

Author Correction: Analog Coding in Emerging Memory Systems.

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111).

Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore's law of the number of transistors in an integrated circuit1. One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering2,3. Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces4 or bulk copper foils5. However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films6,7. Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)5,8 is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.

Gate Quantum Capacitance Effects in Nanoscale Transistors.

As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (CQ). We demonstrate the impact of gate CQ and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. We experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.