Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range.

We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a wide range of gate and drain voltages (Vgs and Vds, respectively). Special attention is paid to the contribution of secondary carriers (generated by impact ionization) to HCD, which was shown to be significant under stress conditions with low Vgs and relatively high Vds. Implementation of this contribution is based on refined modeling of carrier transport for both primary and secondary carriers. To validate the model, we employ foundry-quality n-channel transistors and a broad range of stress voltages {Vgs,Vds}.

High-speed black phosphorus field-effect transistors approaching ballistic limit.

As a strong candidate for future electronics, atomically thin black phosphorus (BP) has attracted great attention in recent years because of its tunable bandgap and high carrier mobility. Here, we show that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation. By designing the device channels along the lower effective mass armchair direction, a record-high drive current up to 1.2 mA/µm at 300 K and 1.6 mA/µm at 20 K can be achieved in a 100-nm back-gated BP transistor, surpassing any two-dimensional semiconductor transistors reported to date. The highest hole saturation velocity of 1.5 × 107 cm/s is also achieved at room temperature. Ballistic transport shows a record-high 36 and 79% ballistic efficiency at room temperature and 20 K, respectively, which is also further verified by theoretical simulations.