Energy-Efficient Neuromorphic Architectures for Nuclear Radiation Detection Applications.

A comprehensive analysis and simulation of two memristor-based neuromorphic architectures for nuclear radiation detection is presented. Both scalable architectures retrofit a locally competitive algorithm to solve overcomplete sparse approximation problems by harnessing memristor crossbar execution of vector-matrix multiplications. The proposed systems demonstrate excellent accuracy and throughput while consuming minimal energy for radionuclide detection. To ensure that the simulation results of our proposed hardware are realistic, the memristor parameters are chosen from our own fabricated memristor devices. Based on these results, we conclude that memristor-based computing is the preeminent technology for a radiation detection platform.

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction.

Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35µm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

Visible (400- to 700-nm) chirped-grating-coupled waveguide spectrometer.

An integrable on-chip spectrometer, based on a transversely-chirped-grating waveguide-coupler for the 400- to 700-nm visible spectral range is demonstrated. For a fixed angle of incidence, the coupling wavelength is dependent on the local grating period and the waveguide structure. The transversely-chirped-input grating is fabricated on a SiO2-Si3N4-SiO2 waveguide atop a Si substrate by interferometric lithography in two sections on a single silicon substrate. A uniform period grating, separated from the input coupler by a propagation region, is provided for out-coupling to a 2048 element CMOS detector array. The incident light with wavelength spanning 400- to 700-nm is coupled into waveguide at 33.5° through the chirped grating coupler. A resolution of ∼ 1.2 nm is demonstrated without any signal processing reconstruction.

Motion-Based Object Location on a Smart Image Sensor Using On-Pixel Memory.

Object location is a crucial computer vision method often used as a previous stage to object classification. Object-location algorithms require high computational and memory resources, which poses a difficult challenge for portable and low-power devices, even when the algorithm is implemented using dedicated digital hardware. Moving part of the computation to the imager may reduce the memory requirements of the digital post-processor and exploit the parallelism available in the algorithm. This paper presents the architecture of a Smart Imaging Sensor (SIS) that performs object location using pixel-level parallelism. The SIS is based on a custom smart pixel, capable of computing frame differences in the analog domain, and a digital coprocessor that performs morphological operations and connected components to determine the bounding boxes of the detected objects. The smart-pixel array implements on-pixel temporal difference computation using analog memories to detect motion between consecutive frames. Our SIS can operate in two modes: (1) as a conventional image sensor and (2) as a smart sensor which delivers a binary image that highlights the pixels in which movement is detected between consecutive frames and the object bounding boxes. In this paper, we present the design of the smart pixel and evaluate its performance using post-parasitic extraction on a 0.35 µm mixed-signal CMOS process. With a pixel-pitch of 32 µm × 32 µm, we achieved a fill factor of 28%. To evaluate the scalability of the design, we ported the layout to a 0.18 µm process, achieving a fill factor of 74%. On an array of 320×240 smart pixels, the circuit operates at a maximum frame rate of 3846 frames per second. The digital coprocessor was implemented and validated on a Xilinx Artix-7 XC7A35T field-programmable gate array that runs at 125 MHz, locates objects in a video frame in 0.614 µs, and has a power consumption of 58 mW.

Face Recognition on a Smart Image Sensor Using Local Gradients.

In this paper, we present the architecture of a smart imaging sensor (SIS) for face recognition, based on a custom-design smart pixel capable of computing local spatial gradients in the analog domain, and a digital coprocessor that performs image classification. The SIS uses spatial gradients to compute a lightweight version of local binary patterns (LBP), which we term ringed LBP (RLBP). Our face recognition method, which is based on Ahonen's algorithm, operates in three stages: (1) it extracts local image features using RLBP, (2) it computes a feature vector using RLBP histograms, (3) it projects the vector onto a subspace that maximizes class separation and classifies the image using a nearest neighbor criterion. We designed the smart pixel using the TSMC 0.35 µm mixed-signal CMOS process, and evaluated its performance using postlayout parasitic extraction. We also designed and implemented the digital coprocessor on a Xilinx XC7Z020 field-programmable gate array. The smart pixel achieves a fill factor of 34% on the 0.35 µm process and 76% on a 0.18 µm process with 32 µm × 32 µm pixels. The pixel array operates at up to 556 frames per second. The digital coprocessor achieves 96.5% classification accuracy on a database of infrared face images, can classify a 150×80-pixel image in 94 µs, and consumes 71 mW of power.

Chirped-grating spectrometer-on-a-chip.

We demonstrate an on-chip spectrometer readily integrable with CMOS electronics. The structure is comprised of a SiO2/Si3N4/SiO2 waveguide atop a silicon substrate. A transversely chirped grating is fabricated, in a single-step optical lithography process, on a portion of the waveguide to provide angle and wavelength dependent coupling to the guided mode. The spectral and angular information is encoded in the spatial dependence of the grating period. A uniform pitch grating area, separated from the collection area by an unpatterned propagation region, provides the out-coupling to a CMOS detector array. A resolution of 0.3 nm at 633 nm with a spectral coverage tunable across the visible and NIR (to ∼ 1 µm limited by the Si photodetector) by changing the angle of incidence, is demonstrated without the need for any signal processing deconvolution. This on-chip spectrometer concept will cost effectively enable a broad range of applications that are beyond the reach of current integrated spectroscopic technologies.

CMOS approach to compressed-domain image acquisition.

A hardware implementation of a real-time compressed-domain image acquisition system is demonstrated. The system performs front-end computational imaging, whereby the inner product between an image and an arbitrarily-specified mask is implemented in silicon. The acquisition system is based on an intelligent readout integrated circuit (iROIC) that is capable of providing independent bias voltages to individual detectors, which enables implementation of spatial multiplication with any prescribed mask through a bias-controlled response-modulation mechanism. The modulated pixels are summed up in the image grabber to generate the compressed samples, namely aperture-coded coefficients, of an image. A rigorous bias-selection algorithm is presented to the readout circuit, which exploits the bias-dependent nature of the imager's responsivity. Proven functionality of the hardware in transform coding compressed image acquisition, silicon-level compressive sampling, in pixel nonuniformity correction and hardware-level implementation of region-based enhancement is demonstrated.

CMOS-compatible plenoptic detector for LED lighting applications.

LED lighting systems with large color gamuts, with multiple LEDs spanning the visible spectrum, offer the potential of increased lighting efficiency, improved human health and productivity, and visible light communications addressing the explosive growth in wireless communications. The control of this "smart lighting system" requires a silicon-integrated-circuit-compatible, visible, plenoptic (angle and wavelength) detector. A detector element, based on an offset-grating-coupled dielectric waveguide structure and a silicon photodetector, is demonstrated with an angular resolution of less than 1° and a wavelength resolution of less than 5 nm.

Breaking the buildup-time limit of sensitivity in avalanche photodiodes by dynamic biasing.

Avalanche photodiodes (APDs) are the preferred photodetectors for direct-detection, high data-rate long-haul optical telecommunications. APDs can detect low-level optical signals due to their internal amplification of the photon-generated electrical current, which is attributable to the avalanche of electron and hole impact ionizations. Despite recent advances in APDs aimed at reducing the average avalanche-buildup time, which causes intersymbol interference and compromises receiver sensitivity at high data rates, operable speeds of commercially available APDs have been limited to 10Gbps. We report the first demonstration of a dynamically biased APD that breaks the traditional sensitivity-versus-speed limit by employing a data-synchronous sinusoidal reverse-bias that drastically suppresses the average avalanche-buildup time. Compared with traditional DC biasing, the sensitivity of germanium APDs at 3Gbps is improved by 4.3 dB, which is equivalent to a 3,500-fold reduction in the bit-error rate. The method is APD-type agnostic and it promises to enable operation at rates of 25Gbps and beyond.

Continuous time-varying biasing approach for spectrally tunable infrared detectors.

In a recently demonstrated algorithmic spectral-tuning technique by Jang et al. [Opt. Express 19, 19454-19472, (2011)], the reconstruction of an object's emissivity at an arbitrarily specified spectral window of interest in the long-wave infrared region was achieved. The technique relied upon forming a weighted superposition of a series of photocurrents from a quantum dots-in-a-well (DWELL) photodetector operated at discrete static biases that were applied serially. Here, the technique is generalized such that a continuously varying biasing voltage is employed over an extended acquisition time, in place using a series of fixed biases over each sub-acquisition time, which totally eliminates the need for the post-processing step comprising the weighted superposition of the discrete photocurrents. To enable this capability, an algorithm is developed for designing the time-varying bias for an arbitrary spectral-sensing window of interest. Since continuous-time biasing can be implemented within the readout circuit of a focal-plane array, this generalization would pave the way for the implementation of the algorithmic spectral tuning in focal-plane arrays within in each frame time without the need for on-sensor multiplications and additions. The technique is validated by means of simulations in the context of spectrometry and object classification while using experimental data for the DWELL under realistic signal-to-noise ratios.

Data compressive paradigm for multispectral sensing using tunable DWELL mid-infrared detectors.

While quantum dots-in-a-well (DWELL) infrared photodetectors have the feature that their spectral responses can be shifted continuously by varying the applied bias, the width of the spectral response at any applied bias is not sufficiently narrow for use in multispectral sensing without the aid of spectral filters. To achieve higher spectral resolutions without using physical spectral filters, algorithms have been developed for post-processing the DWELL's bias-dependent photocurrents resulting from probing an object of interest repeatedly over a wide range of applied biases. At the heart of these algorithms is the ability to approximate an arbitrary spectral filter, which we desire the DWELL-algorithm combination to mimic, by forming a weighted superposition of the DWELL's non-orthogonal spectral responses over a range of applied biases. However, these algorithms assume availability of abundant DWELL data over a large number of applied biases (>30), leading to large overall acquisition times in proportion with the number of biases. This paper reports a new multispectral sensing algorithm to substantially compress the number of necessary bias values subject to a prescribed performance level across multiple sensing applications. The algorithm identifies a minimal set of biases to be used in sensing only the relevant spectral information for remote-sensing applications of interest. Experimental results on target spectrometry and classification demonstrate a reduction in the number of required biases by a factor of 7 (e.g., from 30 to 4). The tradeoff between performance and bias compression is thoroughly investigated.