Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor.

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

Sensing single domains and individual defects in scaled ferroelectrics.

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics.

Correction: Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Correction for 'Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction' by Dmitry Dzhigaev et al., Nanoscale, 2020, 12, 14487-14493, DOI: 10.1039/D0NR02260H.

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III-V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III-V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III-V CMOS technologies.

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing.

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (gm,peak) by 50% among 28 devices and achieved 70µSµm-1atVDS = -0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec-1as well as an off-current below 5 nAµm-1which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device withLg = 80 nm in RTA, which shows an increasedgm,peakup to 149µSµm-1atVDS = -0.5 V as well as a low on-resistance of 4.7 kΩ·µm. The potential of further enhancement ingmvia RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.

Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Semiconductor nanowires in wrapped, gate-all-around transistor geometry are highly favorable for future electronics. The advanced nanodevice processing results in strain due to the deposited dielectric and metal layers surrounding the nanowires, significantly affecting their performance. Therefore, non-destructive nanoscale characterization of complete devices is of utmost importance due to the small feature sizes and three-dimensional buried structure. Direct strain mapping inside heterostructured GaSb-InAs nanowire tunnel field-effect transistor embedded in dielectric HfO2, W metal gate layers, and an organic spacer is performed using fast scanning X-ray nanodiffraction. The effect of 10 nm W gate on a single embedded nanowire with segment diameters down to 40 nm is retrieved. The tensile strain values reach 0.26% in the p-type GaSb segment of the transistor. Supported by the finite element method simulation, we establish a connection between the Ar pressure used during the W layer deposition and the nanowire strain state. Thus, we can benchmark our models for further improvements in device engineering. Our study indicates, how the significant increase in X-ray brightness at 4th generation synchrotron, makes high-throughput measurements on realistic nanoelectronic devices viable.

Ferroelectric Enhanced Performance of a GeSn/Ge Dual-Nanowire Photodetector.

GeSn offers a reduced bandgap than Ge and has been utilized in Si-based infrared photodetectors with an extended cutoff wavelength. However, the traditional GeSn/Ge heterostructure usually consists of defects like misfit dislocations due to the lattice mismatch issue. The defects with the large feature size of a photodetector fabricated on bulk GeSn/Ge heterostructures induce a considerable dark current. Here, we demonstrate a flexible GeSn/Ge dual-nanowire (NW) structure, in which the strain relaxation is achieved by the elastic deformation without introducing defects, and the feature dimension is naturally at the nanoscale. A photodetector with a low dark current can be built on a GeSn/Ge dual-NW, which exhibits an extended detection wavelength beyond 2 µm and enhanced responsivity compared to the Ge NW. Moreover, the dark current can be further suppressed by the depletion effect from the ferroelectric polymer side gate. Our work suggests the flexible GeSn/Ge dual-NW may open an avenue for Si-compatible optoelectronic circuits operating in the short-wavelength infrared range.

InPBi Quantum Dots for Super-Luminescence Diodes.

InPBi thin film has shown ultra-broad room temperature photoluminescence, which is promising for applications in super-luminescent diodes (SLDs) but met problems with low light emission efficiency. In this paper, InPBi quantum dot (QD) is proposed to serve as the active material for future InPBi SLDs. The quantum confinement for carriers and reduced spatial size of QD structure can improve light emission efficiently. We employ finite element method to simulate strain distribution inside QDs and use the result as input for calculating electronic properties. We systematically investigate different transitions involving carriers on the band edges and the deep levels as a function of Bi composition and InPBi QD geometry embedded in InAlAs lattice matched to InP. A flat QD shape with a moderate Bi content of a few percent over 3.2% would provide the optimal performance of SLDs with a bright and wide spectrum at a short center wavelength, promising for future optical coherence tomography applications.

Theoretical Investigation of Biaxially Tensile-Strained Germanium Nanowires.

We theoretically investigate highly tensile-strained Ge nanowires laterally on GaSb. Finite element method has been used to simulate the residual elastic strain in the Ge nanowire. The total energy increment including strain energy, surface energy, and edge energy before and after Ge deposition is calculated in different situations. The result indicates that the Ge nanowire on GaSb is apt to grow along 〈100〉 rather than 〈110〉 in the two situations and prefers to be exposed by {105} facets when deposited a small amount of Ge but to be exposed by {110} when the amount of Ge exceeds a critical value. Furthermore, the conduction band minima in Γ-valley at any position in both situations exhibits lower values than those in L-valley, leading to direct bandgap transition in Ge nanowire. For the valence band, the light hole band maxima at Γ-point is higher than the heavy hole band maxima at any position and even higher than the conduction band minima for the hydrostatic strain more than ∼5.0%, leading to a negative bandgap. In addition, both electron and hole mobility can be enhanced by owing to the decrease of the effective mass under highly tensile strain. The results suggest that biaxially tensile-strained Ge nanowires hold promising properties in device applications.