A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array.

A power and area efficient CMOS stochastic neuron for resistive computing device-based neural networks is presented. The stochastic neuron performs both quantization and activation function simultaneously by using a single dynamic comparator and allows power-hungry analog to digital and digital to analog converters to be removed at the cost of the increased computation time. A network learning method utilizing a noisy sigmoid function is also presented to minimize the computation time with little accuracy degradation. A prototype neuron chip fabricated in 0.18µm CMOS process successfully demonstrates the neuron's performance and the learning method is verified through network simulations.

Electronic system with memristive synapses for pattern recognition.

Memristive synapses, the most promising passive devices for synaptic interconnections in artificial neural networks, are the driving force behind recent research on hardware neural networks. Despite significant efforts to utilize memristive synapses, progress to date has only shown the possibility of building a neural network system that can classify simple image patterns. In this article, we report a high-density cross-point memristive synapse array with improved synaptic characteristics. The proposed PCMO-based memristive synapse exhibits the necessary gradual and symmetrical conductance changes, and has been successfully adapted to a neural network system. The system learns, and later recognizes, the human thought pattern corresponding to three vowels, i.e. /a /, /i /, and /u/, using electroencephalography signals generated while a subject imagines speaking vowels. Our successful demonstration of a neural network system for EEG pattern recognition is likely to intrigue many researchers and stimulate a new research direction.