Reservoir computing with a random memristor crossbar array.

Physical implementations of reservoir computing (RC) based on the emerging memristors have become promising candidates of unconventional computing paradigms. Traditionally, sequential approaches by time-multiplexing volatile memristors have been prevalent because of their low hardware overhead. However, they suffer from the problem of speed degradation and fall short of capturing the spatial relationship between the time-domain inputs. Here, we explore a new avenue for RC using memristor crossbar arrays with device-to-device variations, which serve as physical random weight matrices of the reservoir layers, enabling faster computation thanks to the parallelism of matrix-vector multiplication as an intensive operation in RC. To achieve this new RC architecture, ultralow-current, self-selective memristors are fabricated and integrated without the need of transistors, showing greater potential of high scalability and three-dimensional integrability compared to the previous realizations. The information processing ability of our RC system is demonstrated in asks of recognizing digit images and waveforms. This work indicates that the 'nonidealities' of the emerging memristor devices and circuits are a useful source of inspiration for new computing paradigms.

A crossbar architecture based system (CAS) as hydrogen gas sensing platform.

The development of sensing technologies and miniaturization allows for the development of smart systems with elevated sensing performance. Silicon-based hydrogen sensors have received a lot of attention due to its electrical conductivity and the mechanical endurance. With this motivation, we have proposed a two-terminal silicon-based device in a crossbar architecture as a hydrogen gas sensing platform. In this work, we have adopted a multi-layer modeling approach to analyze the performance of the proposed system. Technology computer-aided design models have been used to capture device performance. A gas sensor model based on hydrogen adsorption on the Palladium surface and a crossbar model has been adopted to understand the Palladium work function variation with gas pressure and the performance of the proposed crossbar system respectively. We have shown the impact of parameters like interconnect resistance and array size on the whole system's performance. Finally, a comprehensive analysis has been provided for the design rule of this architecture. A fabrication process to spur future experimental works has also been added. This work will provide computational insight into the performance of a crossbar hydrogen sensor system, optimized against some critical parameters.

Intrinsic variation effect in memristive neural network with weight quantization.

To analyze the effect of the intrinsic variations of the memristor device on the neuromorphic system, we fabricated 32 × 32 Al2O3/TiOx-based memristor crossbar array and implemented 3 bit multilevel conductance as weight quantization by utilizing the switching characteristics to minimize the performance degradation of the neural network. The tuning operation for 8 weight levels was confirmed with a tolerance of ±4µA (±40µS). The endurance and retention characteristics were also verified, and the random telegraph noise (RTN) characteristics were measured according to the weight range to evaluate the internal stochastic variation effect. Subsequently, a memristive neural network was constructed by off-chip training with differential memristor pairs for the Modified National Institute of Standards and Technology (MNIST) handwritten dataset. The pre-trained weights were quantized, and the classification accuracy was evaluated by applying the intrinsic variations to each quantized weight. The intrinsic variations were applied using the measured weight inaccuracy given by the tuning tolerance, RTN characteristics, and the fault device yield. We believe these results should be considered when the pre-trained weights are transferred to a memristive neural network by off-chip training.

Down-Scalable and Ultra-fast Memristors with Ultra-high Density Three-Dimensional Arrays of Perovskite Quantum Wires.

With strikingly high speed, data retention ability and storage density, resistive RAMs have emerged as a forerunning nonvolatile memory. Here we developed a Re-RAM with ultra-high density array of monocrystalline perovskite quantum wires (QWs) as the switching matrix with a metallic silver conducting pathway. The devices demonstrated high ON/OFF ratio of ∼107 and ultra-fast switching speed of ∼100 ps which is among the fastest in literature. The devices also possess long retention time of over 2 years and record high endurance of ∼6 × 106 cycles for all perovskite Re-RAMs reported. As a concept proof, we have also successfully demonstrated a flexible Re-RAM crossbar array device with a metal-semiconductor-insulator-metal design for sneaky path mitigation, which can store information with long retention. Aggressive downscaling to ∼14 nm lateral dimension produced an ultra-small cell effectively having 76.5 nm2 area for single bit storage. Furthermore, the devices also exhibited unique optical programmability among the low resistance states.

Spatiotemporal Data Processing with Memristor Crossbar-Array-Based Graph Reservoir.

Memristor-based physical reservoir computing (RC) is a robust framework for processing complex spatiotemporal data parallelly. However, conventional memristor-based reservoirs cannot capture the spatial relationship between the time-varying inputs due to the specific mapping scheme assigning one input signal to one memristor conductance. Here, a physical "graph reservoir" is introduced using a metal cell at the diagonal-crossbar array (mCBA) with dynamic self-rectifying memristors. Input and inverted input signals are applied to the word and bit lines of the mCBA, respectively, storing the correlation information between input signals in the memristors. In this way, the mCBA graph reservoirs can map the spatiotemporal correlation of the input data in a high-dimensional feature space. The high-dimensional mapping characteristics of the graph reservoir achieve notable results, including a normalized root-mean-square error of 0.09 in Mackey-Glass time series prediction, a 97.21% accuracy in MNIST recognition, and an 80.0% diagnostic accuracy in human connectome classification.

Efficient Data Transfer and Multi-Bit Multiplier Design in Processing in Memory.

Processing in Memory based on memristors is considered the most effective solution to overcome the Von Neumann bottleneck issue and has become a hot research topic. The execution efficiency of logical computation and in-memory data transmission is crucial for Processing in Memory. This paper presents a design scheme for data transmission and multi-bit multipliers within MAT (a data storage set in MPU) based on the memristive alternating crossbar array structure. Firstly, to improve the data transfer efficiency, we reserve the edge row and column of the array as assistant cells for OR AND (OA) and AND data transmission logic operations to reduce the data transfer steps. Furthermore, we convert the multipliers into multi-bit addition operations via Multiple Input Multiple Output (MIMO) logical operations, which effectively improves the execution efficiency of multipliers. PSpice simulation shows that the proposed data transmission and multi-bit multiplier solution has lower latency and power consumption and higher efficiency and flexibility.

Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials.

The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.

Memristive Architectures Exploiting Self-Compliance Multilevel Implementation on 1 kb Crossbar Arrays for Online and Offline Learning Neuromorphic Applications.

This paper suggests the practical implications of utilizing a high-density crossbar array with self-compliance (SC) at the conductive filament (CF) formation stage. By limiting the excessive growth of CF, SC functions enable the operation of a crossbar array without access transistors. An AlOx/TiOy, internal overshoot limitation structure, allows the SC to have resistive random-access memory. In addition, an overshoot-limited memristor crossbar array makes it possible to implement vector-matrix multiplication (VMM) capability in neuromorphic systems. Furthermore, AlOx/TiOy structure optimization was conducted to reduce overshoot and operation current, verifying uniform bipolar resistive switching behavior and analog switching properties. Additionally, extensive electric pulse stimuli are confirmed, evaluating long-term potentiation (LTP), long-term depression (LTD), and other forms of synaptic plasticity. We found that LTP and LTD characteristics for training an online learning neural network enable MNIST classification accuracies of 92.36%. The SC mode quantized multilevel in offline learning neural networks achieved 95.87%. Finally, the 32 × 32 crossbar array demonstrated spiking neural network-based VMM operations to classify the MNIST image. Consequently, weight programming errors make only a 1.2% point of accuracy drop to software-based neural networks.

Oscillatory Neural Network-Based Ising Machine Using 2D Memristors.

Neural networks are increasingly used to solve optimization problems in various fields, including operations research, design automation, and gene sequencing. However, these networks face challenges due to the nondeterministic polynomial time (NP)-hard issue, which results in exponentially increasing computational complexity as the problem size grows. Conventional digital hardware struggles with the von Neumann bottleneck, the slowdown of Moore's law, and the complexity arising from heterogeneous system design. Two-dimensional (2D) memristors offer a potential solution to these hardware challenges, with their in-memory computing, decent scalability, and rich dynamic behaviors. In this study, we explore the use of nonvolatile 2D memristors to emulate synapses in a discrete-time Hopfield neural network, enabling the network to solve continuous optimization problems, like finding the minimum value of a quadratic polynomial, and tackle combinatorial optimization problems like Max-Cut. Additionally, we coupled volatile memristor-based oscillators with nonvolatile memristor synapses to create an oscillatory neural network-based Ising machine, a continuous-time analog dynamic system capable of solving combinatorial optimization problems including Max-Cut and map coloring through phase synchronization. Our findings demonstrate that 2D memristors have the potential to significantly enhance the efficiency, compactness, and homogeneity of integrated Ising machines, which is useful for future advances in neural networks for optimization problems.

Threshold learning algorithm for memristive neural network with binary switching behavior.

On-chip learning is an effective method for adjusting artificial neural networks in neuromorphic computing systems by considering hardware intrinsic properties. However, it faces challenges due to hardware nonidealities, such as the nonlinearity of potentiation and depression and limitations on fine weight adjustment. In this study, we propose a threshold learning algorithm for a variation-tolerant ternary neural network in a memristor crossbar array. This algorithm utilizes two tightly separated resistance states in memristive devices to represent weight values. The high-resistance state (HRS) and low-resistance state (LRS) defined as read current of < 0.1 µA and > 1 µA, respectively, were successfully programmed in a 32 × 32 crossbar array, and exhibited half-normal distributions due to the programming method. To validate our approach experimentally, a 64 × 10 single-layer fully connected network were trained in the fabricated crossbar for an 8 × 8 MNIST dataset using the threshold learning algorithm, where the weight value is updated when a gradient determined by backpropagation exceeds a threshold value. Thanks to the large margin between the two states of the memristor, we observed only a 0.42 % drop in classification accuracy compared to the baseline network results. The threshold learning algorithm is expected to alleviate the programming burden and be utilized in variation-tolerant neuromorphic architectures.

Memristive Crossbar Array-Based Probabilistic Graph Modeling.

Modern graph datasets with structural complexity and uncertainties due to incomplete information or data variability require advanced modeling techniques beyond conventional graph models. This study introduces a memristive crossbar array (CBA)-based probabilistic graph model (C-PGM) utilizing Cu0.3Te0.7/HfO2/Pt memristors, which exhibit probabilistic switching, self-rectifying, and memory characteristics. C-PGM addresses the complexities and uncertainties inherent in structural graph data across various domains, leveraging the probabilistic nature of memristors. C-PGM relies on the device-to-device variation across multiple memristive CBAs, overcoming the limitations of previous approaches that rely on sequential operations, which are slower and have a reliability concern due to repeated switching. This new approach enables the fast processing and massive implementation of probabilistic units at the expense of chip area. In this study, the hardware-based C-PGM feasibly expresses small-scale probabilistic graphs and shows minimal error in aggregate probability calculations. The probability calculation capabilities of C-PGM are applied to steady-state estimation and the PageRank algorithm, which is implemented on a simulated large-scale C-PGM. The C-PGM-based steady-state estimation and PageRank algorithm demonstrate comparable accuracy to conventional methods while significantly reducing computational costs.

Eco-Friendly Biomemristive Nonvolatile Memory: Harnessing Organic Waste for Sustainable Technology.

Organic material-based bioelectronic nonvolatile memory devices have recently received a lot of attention due to their environmental compatibility, simple fabrication recipe, preferred scalability, low cost, low power consumption, and numerous additional advantages. Resistive random-access memory (RRAM) devices work on the principle of resistive switching, which has the potential for applications in memory storage and neuromorphic computing. Here, natural organically grown orange peel was used to extract biocompatible pectin to design a resistive switching-based memory device of the structure Ag/Pectin/Indium tin oxide (ITO), and the behavior was studied between a temperature range of 10K and 300K. The microscopic characterization revealed the texture of the surface and thickness of the layers. The memristive current-voltage characteristics performed over 1000 consecutive cycles of repeated switching revealed sustainable bipolar resistive switching behavior with a high ON/OFF ratio. The underlying principle of Resistive Switching behavior is based on the formation of conductive filaments between the electrodes, which is explained in this work. Further, we have also designed a 2 × 2 crossbar array of RRAM devices to demonstrate various logic circuit operations useful for neuromorphic computing. The robust switching characteristics suggest possible uses of such devices for the design of ecofriendly bioelectronic memory applications and in-memory computing.

Cross-Wired Memristive Crossbar Array for Effective Graph Data Analysis.

Graphs adequately represent the enormous interconnections among numerous entities in big data, incurring high computational costs in analyzing them with conventional hardware. Physical graph representation (PGR) is an approach that replicates the graph within a physical system, allowing for efficient analysis. This study introduces a cross-wired crossbar array (cwCBA), uniquely connecting diagonal and non-diagonal components in a CBA by a cross-wiring process. The cross-wired diagonal cells enable cwCBA to achieve precise PGR and dynamic node state control. For this purpose, a cwCBA is fabricated using Pt/Ta2O5/HfO2/TiN (PTHT) memristor with high on/off and self-rectifying characteristics. The structural and device benefits of PTHT cwCBA for enhanced PGR precision are highlighted, and the practical efficacy is demonstrated for two applications. First, it executes a dynamic path-finding algorithm, identifying the shortest paths in a dynamic graph. PTHT cwCBA shows a more accurate inferred distance and ≈1/3800 lower processing complexity than the conventional method. Second, it analyzes the protein-protein interaction (PPI) networks containing self-interacting proteins, which possess intricate characteristics compared to typical graphs. The PPI prediction results exhibit an average of 30.5% and 21.3% improvement in area under the curve and F1-score, respectively, compared to existing algorithms.

Multiphase Reset Induced Reliable Dual-Mode Resistance Switching of the Ta/HfO2/RuO2 Memristor.

Higher functionality should be achieved within the device-level switching characteristics to secure the operational possibility of mixed-signal data processing within a memristive crossbar array. This work investigated electroforming-free Ta/HfO2/RuO2 resistive switching devices for digital- and analog-type applications through various structural and electrical analyses. The multiphase reset behavior, induced by the conducting filament modulation and oxygen vacancy generation (annihilation) in the HfO2 layer by interacting with the Ta (RuO2) electrode, was utilized for the switching mode change. Therefore, a single device can manifest stable binary switching between low and high resistance states for the digital mode and the precise 8-bit conductance modulation (256 resistance values) via an optimized pulse application for the analog mode. An in-depth analysis of the operation in different modes and comparing memristors with different electrode structures validate the proposed mechanism. The Ta/HfO2/RuO2 resistive switching device is feasible for a mixed-signal processable memristive array.

Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization.

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its estimated gradient. Additionally, we adopt a fixed kernel method, where inputs are sequentially applied to a crossbar array with a differential memristor pair scheme, reducing unused cell waste. The binary activation has robust characteristics against device state variations, and a neuron circuit is experimentally demonstrated on a customized breadboard. Thanks to the analogue switching characteristics of the memristor device, the accurate vector-matrix multiplication (VMM) operations can be experimentally demonstrated by combining sequential inputs and the weights obtained through tuning operations in the crossbar array. In addition, the feature images extracted by VMM during the hardware inference operations on 100 test samples are classified, and the classification performance by off-chip training is compared with the software results. Finally, inference results depending on the tolerance are statistically verified through several tuning cycles.

Enhancing the Uniformity of a Memristor Using a Bilayer Dielectric Structure.

Resistive random access memory (RRAM) holds great promise for in-memory computing, which is considered the most promising strategy for solving the von Neumann bottleneck. However, there are still significant problems in its application due to the non-uniform performance of RRAM devices. In this work, a bilayer dielectric layer memristor was designed based on the difference in the Gibbs free energy of the oxide. We fabricated Au/Ta2O5/HfO2/Ta/Pt (S3) devices with excellent uniformity. Compared with Au/HfO2/Pt (S1) and Au/Ta2O5/Pt (S2) devices, the S3 device has a low reset voltage fluctuation of 2.44%, and the resistive coefficients of variation are 13.12% and 3.84% in HRS and LRS, respectively, over 200 cycles. Otherwise, the bilayer device has better linearity and more conductance states in multi-state regulation. At the same time, we analyze the physical mechanism of the bilayer device and provide a physical model of ion migration. This work provides a new idea for designing and fabricating resistive devices with stable performance.

A Design Methodology for Fault-Tolerant Neuromorphic Computing Using Bayesian Neural Network.

Memristor crossbar arrays are a promising platform for neuromorphic computing. In practical scenarios, the synapse weights represented by the memristors for the underlying system are subject to process variations, in which the programmed weight when read out for inference is no longer deterministic but a stochastic distribution. It is therefore highly desired to learn the weight distribution accounting for process variations, to ensure the same inference performance in memristor crossbar arrays as the design value. In this paper, we introduce a design methodology for fault-tolerant neuromorphic computing using a Bayesian neural network, which combines the variational Bayesian inference technique with a fault-aware variational posterior distribution. The proposed framework based on Bayesian inference incorporates the impacts of memristor deviations into algorithmic training, where the weight distributions of neural networks are optimized to accommodate uncertainties and minimize inference degradation. The experimental results confirm the capability of the proposed methodology to tolerate both process variations and noise, while achieving more robust computing in memristor crossbar arrays.

Amorphous ITZO-Based Selector Device for Memristor Crossbar Array.

In the era of digital transformation, a memristor and memristive circuit can provide an advanced computer architecture that efficiently processes a vast quantity of data. With the unique characteristic of memristor, a memristive crossbar array has been utilized for realization of nonvolatile memory, logic-in-memory circuit, and neuromorphic system. However, the crossbar array architecture suffers from leakage of current, known as the sneak current, which causes a cross-talk interference problem between adjacent memristor devices, leading to an unavoidable operational error and high power consumption. Here, we present an amorphous In-Sn-Zn-O (a-ITZO) oxide semiconductor-based selector device to address the sneak current issue. The a-ITZO-selector device is realized with the back-to-back Schottky diode with nonlinear current-voltage (I-V) characteristics. Its nonlinearity is dependent on the oxygen plasma treatment process which can suppress the surface electron accumulation layer arising on the a-ITZO surface. The a-ITZO-selector device shows reliable characteristics against electrical stress and high temperature. In addition, the selector device allows for a stable read margin over 1 Mbit of memristor crossbar array. The findings may offer a feasible solution for the development of a high-density memristor crossbar array.

Highly Reliable Ovonic Threshold Switch with TiN/GeTe/TiN Structure.

A new architecture has become necessary owing to the power consumption and latency problems of the von Neumann architecture. A neuromorphic memory system is a promising candidate for the new system as it has the potential to process large amounts of digital information. A crossbar array (CA), which consists of a selector and a resistor, is the basic building block for the new system. Despite the excellent prospects of crossbar arrays, the biggest obstacle for them is sneak current, which can cause a misreading between the adjacent memory cells, thus resulting in a misoperation in the arrays. The chalcogenide-based ovonic threshold switch (OTS) is a powerful selector with highly nonlinear I-V characteristics that can be used to address the sneak current problem. In this study, we evaluated the electrical characteristics of an OTS with a TiN/GeTe/TiN structure. This device shows nonlinear DC I-V characteristics, an excellent endurance of up to 109 in the burst read measurement, and a stable threshold voltage below 15 mV/dec. In addition, at temperatures below 300 °C, the device exhibits good thermal stability and retains an amorphous structure, which is a strong indication of the aforementioned electrical characteristics.

Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing.

The progress of artificial intelligence and the development of large-scale neural networks have significantly increased computational costs and energy consumption. To address these challenges, researchers are exploring low-power neural network implementation approaches and neuromorphic computing systems are being highlighted as potential candidates. Specifically, the development of high-density and reliable synaptic devices, which are the key elements of neuromorphic systems, is of particular interest. In this study, an 8 × 16 memcapacitor crossbar array that combines the technological maturity of flash cells with the advantages of NAND flash array structure is presented. The analog properties of the array with high reliability are experimentally demonstrated, and vector-matrix multiplication with extremely low error is successfully performed. Additionally, with the capability of weight fine-tuning characteristics, a spiking neural network for CIFAR-10 classification via off-chip learning at the wafer level is implemented. These experimental results demonstrate a high level of accuracy of 92.11%, with less than a 1.13% difference compared to software-based neural networks (93.24%).