First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates.

A novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) with self-aligned and replaced high-κ metal gates (HKMGs) is presented for the first time, aiming at a 3 nm technology node and beyond. The nVSAFETs were fabricated by an integration flow of Si/SiGe epitaxy, quasi-atomic layer etching (qALE) of SiGe selective to Si, formation of SiGe/Si core/shell NS/NW structure, building of nitride dummy gate, and replacement of the dummy gate. This fabrication method is complementary metal oxide semiconductor (CMOS)-compatible, simple, and reproducible, and NWs with a diameter of 17 nm and NSs with a thickness of 20 nm were obtained. Excellent control of short-channel-effects was presented. The device performance was also investigated and discussed. The proposed integration scheme has great potential for applications in chip manufacturing, especially with vertical channel devices.

A rhodium-catalysed conjugate addition/cyclization cascade for the asymmetric synthesis of 2-amino-4H-chromenes.

The enantioselective synthesis of 2-amino-4H-chromenes via the cascade rhodium-catalysed conjugate addition/hetero Thorpe-Ziegler reaction is reported. Moderate to good yields (up to 98%) and high enantioselectivities (up to 92% ee) were obtained with a chiral diene-coordinated rhodium complex as the catalyst. This protocol remedies the methodological deficiency in the asymmetric synthesis of 4-aryl 2-amino-4H-chromenes.

Atom Probe Tomography Characterization of Dopant Distributions in Si FinFET: Challenges and Solutions.

Atom probe tomography (APT) has emerged as an important tool in characterizing three-dimensional semiconductor devices. However, the complex structure and hybrid nature of a semiconductor device can pose serious challenges to the accurate measurement of dopants. In particular, local magnification and trajectory aberration observed when analyzing hybrid materials with different evaporation fields can cause severe distortions in reconstructed geometry and uncertainty in local chemistry measurement. To address these challenges, this study systematically investigates the effect of APT sampling directions on the measurement of n-type dopants P and As in an Si fin field-effect transistor (FinFET). We demonstrate that the APT samples made with their Z-axis perpendicular to the center axis of the fin are effective to minimize the negative effects that result from evaporation field differences between the Si fin and SiO2 on reconstruction and achieve improved measurement of dopant distributions. In addition, new insights have been gained regarding the distribution of ion-implanted P and As in the Si FinFET.

An umpolung strategy for chemically selective intermolecular cross-enolate-type coupling of N-alkenoxypyridinium salts with aldehydes.

An efficient method for the synthesis of 1,4-ketoaldehydes via the cross-coupling of N-alkenoxyheteroarenium salts and primary aldehydes is developed. This method provides a broad substrate scope and excellent functional group compatibility. The utility of this method is demonstrated via the diverse transformations of heterocyclic compounds and cycloheptanone, as well as the late-stage functionalization of biorelevant molecules.

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control". A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an "exposed top" structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance.

A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of ∼291 µA/µm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.

Rhodium-Catalyzed Chemodivergent Pyridylation of Alkynes with Pyridylboronic Acids.

The pyridylation of alkynes with pyridylboronic acids is realized under rhodium catalysis. Chemodivergent pyridylation products, including alkenylpyridines produced via the hydropyridylation pathway and cyclopenta[c]pyridines produced via the pyridylation/cyclization pathway, were selectively produced by fine-tuning the reaction conditions. A mechanistic study revealed that 1,4-rhodium migration to the pyridine ring was involved as the key step in the chemodivergent synthesis.

Investigation on Ge0.8Si0.2-Selective Atomic Layer Wet-Etching of Ge for Vertical Gate-All-Around Nanodevice.

For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge0.8Si0.2-selective etching of Ge and crystal-orientation selectivity of Ge oxidation, has been developed to control the etch rate and the size of the Ge nanowires. The ALE of Ge in p+-Ge0.8Si0.2/Ge stacks with 70% HNO3 as oxidizer and deionized (DI) water as oxide-removal was investigated in detail. The saturated relative etched amount per cycle (REPC) and selectivity at different HNO3 temperatures between Ge and p+-Ge0.8Si0.2 were obtained. In p+-Ge0.8Si0.2/Ge stacks with (110) sidewalls, the REPC of Ge was 3.1 nm and the saturated etching selectivity was 6.5 at HNO3 temperature of 20 °C. The etch rate and the selectivity were affected by HNO3 temperatures. As the HNO3 temperature decreased to 10 °C, the REPC of Ge was decreased to 2 nm and the selectivity remained at about 7.4. Finally, the application of ALE in the formation of Ge nanowires in vGAAFETs was demonstrated where the preliminary Id-Vds output characteristic curves of Ge vGAAFET were provided.

The Effect of Doping on the Digital Etching of Silicon-Selective Silicon-Germanium Using Nitric Acids.

Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon-germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO3) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO3 digital etching of SiGe was selective to n+-Si, p+-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO3 concentration. As a result, at 31.5% HNO3 concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si0.72Ge0.28 for n+-Si was identical to that for p+-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n+ and p+ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility.

Surface Modification of Monolayer MoS2 by Baking for Biomedical Applications.

Molybdenum disulfide (MoS2), a transition metal dichalcogenide material, possesses great potential in biomedical applications such as chemical/biological sensing, drug/gene delivery, bioimaging, phototherapy, and so on. In particular, monolayer MoS2 has more extensive applications because of its superior physical and chemical properties; for example, it has an ultra-high surface area, is easily modified, and has high biodegradability. It is important to prepare advanced monolayer MoS2 with enhanced energy exchange efficiency (EEE) for the development of MoS2-based nanodevices and therapeutic strategies. In this work, a monolayer MoS2 film was first synthesized through a chemical vapor deposition method, and the surface of MoS2 was further modified via a baking process to develop p-type doping of monolayer MoS2 with high EEE, followed by confirmation by X-ray photoelectron spectroscopy and Raman spectroscopy analysis. The morphology, surface roughness, and layer thickness of monolayer MoS2 before and after baking were thoroughly investigated using atomic force microscopy. The results showed that the surface roughness and layer thickness of monolayer MoS2 modified by baking were obviously increased in comparison with MoS2 without baking, indicating that the surface topography of the monolayer MoS2 film was obviously influenced. Moreover, a photoluminescence spectrum study revealed that p-type doping of monolayer MoS2 displayed much greater photoluminescence ability, which was taken as evidence of higher photothermal conversion efficiency. This study not only developed a novel MoS2 with high EEE for future biomedical applications but also demonstrated that a baking process is a promising way to modify the surface of monolayer MoS2.

Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon-Germanium Multilayers Structures for Vertical Transistors Application.

Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/high-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium.

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

Selective Digital Etching of Silicon-Germanium Using Nitric and Hydrofluoric Acids.

A digital etching method was proposed to achieve excellent control of etching depth. The digital etching characteristics of p+-Si and Si0.7Ge0.3 using a combination of HNO3 oxidation and buffered oxide etching oxide removal processes were investigated. Experimental results showed that oxidation saturates as time goes on because of low activation energy and its diffusion-limited characteristic. An oxidation model was developed to describe the wet oxidation process with nitric acid. The model was calibrated with experimental data, and the oxidation saturation time, final oxide thickness, and selectivity between Si0.7Ge0.3 and p+-Si were obtained. In Si0.7Ge0.3/p+-Si stacks, the saturated relative etched depth per cycle was 0.5 nm (four monolayers), and variation between experiments was about 4% after saturation. A corrected selectivity calculation formula was also proposed, and the calculated selectivity was 3.7-7.7 for different oxidation times, which was the same as the selectivity obtained from our oxidation model. The proposed model can be used to analyze process variations and repeatability, and it can provide credible guidance for the design of other wet digital etching experiments.

State of the Art and Future Perspectives in Advanced CMOS Technology.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors.

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology.

In this paper, pMOSFETs featuring atomic layer deposition (ALD) tungsten (W) using SiH4 and B2H6 precursors in 22 nm node CMOS technology were investigated. It is found that, in terms of threshold voltage, driving capability, carrier mobility, and the control of short-channel effects, the performance of devices featuring ALD W using SiH4 is superior to that of devices featuring ALD W using B2H6. This disparity in device performance results from different metal gate-induced strain from ALD W using SiH4 and B2H6 precursors, i.e. tensile stresses for SiH4 (~2.4 GPa) and for B2H6 (~0.9 GPa).

Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors.

In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective Si1-x Ge x growth (0.35 ≤ × ≤ 0.40) with boron concentration of 1-3 × 1020 cm-3 was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance.

Enhanced End-Contacts by Helium Ion Bombardment to Improve Graphene-Metal Contacts.

Low contact resistance between graphene and metals is of paramount importance to fabricate high performance graphene-based devices. In this paper, the impact of both defects induced by helium ion (He⁺) bombardment and annealing on the contact resistance between graphene and various metals (Ag, Pd, and Pt) were systematically explored. It is found that the contact resistances between all metals and graphene are remarkably reduced after annealing, indicating that not only chemically adsorbed metal (Pd) but also physically adsorbed metals (Ag and Pt) readily form end-contacts at intrinsic defect locations in graphene. In order to further improve the contact properties between Ag, Pd, and Pt metals and graphene, a novel method in which self-aligned He⁺ bombardment to induce exotic defects in graphene and subsequent thermal annealing to form end-contacts was proposed. By using this method, the contact resistance is reduced significantly by 15.1% and 40.1% for Ag/graphene and Pd/graphene contacts with He⁺ bombardment compared to their counterparts without He⁺ bombardment. For the Pt/graphene contact, the contact resistance is, however, not reduced as anticipated with He⁺ bombardment and this might be ascribed to either inappropriate He⁺ bombardment dose, or inapplicable method of He⁺ bombardment in reducing contact resistance for Pt/graphene contact. The joint efforts of as-formed end-contacts and excess created defects in graphene are discussed as the cause responsible for the reduction of contact resistance.