A Mixture of Negative-, Zero-, and Positive-Differential Transconductance Switching from Tellurium/Indium Gallium Zinc Oxide Heterostructures.

Conventional transistors have long emphasized signal modulation and amplification, often sidelining polarity considerations. However, the recent emergence of negative differential transconductance, characterized by a drain current decline during gate voltage sweeping, has illuminated an unconventional path in transistor technology. This phenomenon promises to simplify the implementation of ternary logic circuits and enhance energy efficiency, especially in multivalued logic applications. Our research has culminated in the development of a sophisticated mixed transconductance transistor (M-T device) founded on a precise Te and IGZO heterojunction. The M-T device exhibits a sequence of intriguing phenomena, zero differential transconductance (ZDT), positive differential transconductance (PDT), and negative differential transconductance (NDT) contingent on applied gate voltage. We clarify its operation using a three-segment equivalent circuit model and validate its viability with IGZO TFT, Te TFT, and Te/IGZO TFT components. In a concluding demonstration, the M-T device interconnected with Te TFT achieves a ternary inverter with an intermediate logic state. Remarkably, this configuration seamlessly transitions into a binary inverter when it is exposed to light.

Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.

Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n-type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on-chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non-idealities such as drifting references and long-term retention loss is proposed, demonstrating the importance of device-algorithm co-optimization.

Readily Accessible Metallic Micro-Island Arrays for High-Performance Metal Oxide Thin-Film Transistors.

Thin-film transistors using metal oxide semiconductors are essential in many unconventional electronic devices. Nevertheless, further advances will be necessary to broaden their technological appeal. Here, a new strategy is reported to achieve high-performance solution-processed metal oxide thin-film transistors (MOTFTs) by introducing a metallic micro-island array (M-MIA) on top of the MO back channel, where the MO is a-IGZO (amorphous indium-gallium-zinc-oxide). Here Al-MIAs are fabricated using honeycomb cinnamate cellulose films, created by a scalable breath-figure method, as a shadow mask. For IGZO TFTs, the electron mobility (µe ) increases from ≈3.6 cm2 V-1 s-1 to near 15.6 cm2 V-1 s-1 for optimal Al-MIA dimension/coverage of 1.25 µm/51%. The Al-MIA IGZO TFT performance is superior to that of controls using compact/planar Al layers (Al-PL TFTs) and Au-MIAs with the same channel coverage. Kelvin probe force microscopy and technology computer-aided design simulations reveal that charge transfer occurs between the Al and the IGZO channel which is optimized for specific Al-MIA dimensions/surface channel coverages. Furthermore, such Al-MIA IGZO TFTs with a high-k fluoride-doped alumina dielectric exhibit a maximum µe of >50.2 cm2 V-1 s-1 . This is the first demonstration of a micro-structured MO semiconductor heterojunction with submicrometer resolution metallic arrays for enhanced transistor performance and broad applicability to other devices.

Flexible Light-to-Frequency Conversion Circuits Built with Si-Based Frequency-to-Digital Converters via Complementary Photosensitive Ring Oscillators with p-Type SWNT and n-Type a-IGZO Thin Film Transistors.

In this study, as system-level photodetectors, light-to-frequency conversion circuits (LFCs) are realized by i) photosensitive ring oscillators (ROs) composed of amorphous indium-gallium-zinc-oxide/single-walled carbon nanotube (a-IGZO/SWNT) thin film transistors (TFTs) and ii) phase-locked-loop Si circuits built with frequency-to-digital converters (PFDC). The 3-stage ROs and logic gates based on a-IGZO/SWNT TFTs successfully demonstrate its performance on flexible substrates. Herein, along with the advantage of scalability, a-IGZO films are used as photosensitive n-type TFTs and SWNTs are employed as photo-insensitive p-type TFTs for better photosensitivity in circuit level. Through the controlling a post-annealing condition of a-IGZO film, responsivities and detectivities of a-IGZO TFTs are obtained as 36 AW-1 and 0.3 × 1012 Jones for red, 93 AW-1 and 3.1 × 1012 Jones for green, and 194 AW-1 and 11.7 × 1012 Jones for blue. Furthermore, as an advanced demonstration for practical application of LFCs, a unique circuit (i.e., PFDC) is designed to analyze the generated oscillation frequency (fosc ) from the LFC device and convert it to a digital code. As a result, the designed PFDC can exactly count the generated fosc from the flexible a-IGZO/SWNT ROs under light illumination with an outstanding sensitivity and assign input frequencies to respective digital code.