An Active-Matrix Organic Light-Emitting Diode Pixel Circuit Featuring Mobility Compensation for Portable Applications.

A 6T1C pixel circuit based on low-temperature polycrystalline oxide (LTPO) technology for portable active-matrix organic light-emitting diode (AMOLED) display applications is proposed in this paper. For superior high-end portable applications including 4K high resolution and high PPI (pixels per inch), the proposed pixel circuit employs a single storage capacitor and signal sharing switch-control design and provides low-voltage driving and immunity to the IR-drop issue and OLED degradation. Furthermore, the threshold voltage and mobility-compensating capabilities are improved by both compensation mechanisms, which are based on a negative feedback system, and mobility-related compensation parameters. Simulation results reveal that threshold voltage variations of ±0.33 V in the driving thin-film transistors can be well sensed and compensated while the maximum OLED current shift is 4.25%. The maximum variation in OLED currents within all gray levels is only 1.05% with mobility variations of ±30%. As a result, the proposed 6T1C pixel circuit is a good candidate for portable AMOLED display usage.

AMOLED Pixel Circuit Using LTPO Technology Supporting Variable Frame Rate from 1 to 120 Hz for Portable Displays.

This paper proposes a new 6T1C pixel circuit based on low-temperature polycrystalline oxide (LTPO) technology for portable active-matrix organic light-emitting diode (AMOLED) displays with variable refresh rates ranging from 1 to 120 Hz. The proposed circuit has a simple structure and is based on the design of sharing lines of switch-controlling signals. It also provides low-voltage driving and immunity to OLED degeneration issues. The calculation and analysis of programming time are discussed, and the optimal storage capacitor for the proposed circuit's high-speed driving is selected. The results of the simulation reveal that threshold voltage variations in driving thin-film transistors of ±0.33 V can be well sensed and compensated with a 1.8% average shift of OLED currents in high-frame-rate operation (120 Hz), while the maximum variation in OLED currents within all gray levels is only 3.56 nA in low-frame-rate operation (1 Hz). As a result, the proposed 6T1C pixel circuit is a good candidate for use in portable AMOLED displays.

New Low-Frame-Rate Compensating Pixel Circuit Based on Low-Temperature Poly-Si and Oxide TFTs for High-Pixel-Density Portable AMOLED Displays.

A new low-frame-rate active-matrix organic light-emitting diode (AMOLED) pixel circuit with low-temperature poly-Si and oxide (LTPO) thin-film transistors (TFTs) for portable displays with high pixel density is reported. The proposed pixel circuit has the excellent ability to compensate for the threshold voltage variation of the driving TFT (ΔVTH_DTFT). By the results of simulation based on a fabricated LTPS TFT and a-IZTO TFT, we found that the error rates of the OLED current were all lower than 2.71% over the range of input data voltages when ΔVTH_DTFT = ±0.33 V, and a low frame rate of 1 Hz could be achieved with no flicker phenomenon. Moreover, with only one capacitor and two signal lines in the pixel circuit, a high pixel density and narrow bezel are expected to be realized. We revealed that the proposed 7T1C pixel circuit with low driving voltage and low frame rate is suitable for portable displays.

Performance Enhancement of Pentacene-Based Organic Thin-Film Transistors Using a High-K PVA/Low-K PVP Bilayer as the Gate Insulator.

In this study, we proposed using the high-K polyvinyl alcohol (PVA)/low-K poly-4-vinylphenol (PVP) bilayer structure as the gate insulator to improve the performance of a pentacene-based organic thin-film transistor. The dielectric constant of the optimal high-K PVA/low-K PVP bilayer was 5.6, which was higher than that of the single PVP layer. It resulted in an increase in the gate capacitance and an increased drain current. The surface morphology of the bilayer gate dielectric could be suitable for pentacene grain growth because the PVP layer was deposited above the organic PVA surface, thereby replacing the inorganic surface of the ITO gate electrode. The device performances were significantly improved by using the bilayer gate dielectric based upon the high-K characteristics of the PVA layer and the enlargement of the pentacene grain. Notably, the field-effect mobility was increased from 0.16 to 1.12 cm2/(Vs), 7 times higher than that of the control sample.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment.

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device's reliability.

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

Effects of the F4TCNQ-Doped Pentacene Interlayers on Performance Improvement of Top-Contact Pentacene-Based Organic Thin-Film Transistors.

In this paper, the top-contact (TC) pentacene-based organic thin-film transistor (OTFT) with a tetrafluorotetracyanoquinodimethane (F4TCNQ)-doped pentacene interlayer between the source/drain electrodes and the pentacene channel layer were fabricated using the co-evaporation method. Compared with a pentacene-based OTFT without an interlayer, OTFTs with an F4TCNQ:pentacene ratio of 1:1 showed considerably improved electrical characteristics. In addition, the dependence of the OTFT performance on the thickness of the F4TCNQ-doped pentacene interlayer is weaker than that on a Teflon interlayer. Therefore, a molecular doping-type F4TCNQ-doped pentacene interlayer is a suitable carrier injection layer that can improve the TC-OTFT performance and facilitate obtaining a stable process window.

Teflon/SiO2 Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process.

This study proposes a two-photomask process for fabricating amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES) layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon) and SiO2 combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO2 deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity.

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme.

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm²/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.