InP Crystal Phase Heterojunction Transistor with a Vertical Gate-All-Around Structure.

Crystal phase transitions can form a new type of heterojunction with different atomic arrangements in the same material: crystal phase heterojunction (CPHJ). The CPHJ has an inherently strong impact on band engineering without concerns over critical thicknesses with misfit dislocations and a semiconductor-metal transition. In-plane CPHJ was recently demonstrated in two-dimensional (2D) transition-metal dichalcogenide (TMD) materials and utilized for conventional planar field-effect transistor applications. However, scalability such as gate electrostatic control, miniaturization, and multigate structure have been limited because of the geometrical issue. Here, we demonstrated a transistor using the CPHJ with a vertical gate-all-around structure by forming a CPHJ in conventional III-V semiconductors. The CPHJ, composed of wurtzite InP nanowires with zincblende InP substrates, showed an atomically flat heterojunction without dislocations and indicated a Type-II band discontinuity across the junction. The CPHJ transistor had moderate to good gate electrostatic controllability with high on-state currents and transconductance. The CPHJ offer will provide a new switching mechanism and add a new junction and device design choice to the long history of transistors.

Size control of InP nanowires byin situannealing and its application to the formation of InAsP quantum dots.

We carried outin situannealing of InP nanowires (NWs) in a metal-organic vapor phase epitaxial (MOVPE) growth reactor to control and reduce the tip size of InP NWs. InP NWs were grown by selective-area (SA) MOVPE on partially masked (111)A InP substrates, and annealing was successively applied in tertiarybutylphosphine (TBP) ambient. Initially, the InP NWs had a hexagonal cross-section with{112¯}facets vertical to the substrates; they became tapered, and the edges were rounded by annealing. By appropriately selecting the annealing temperature and initial NW diameter, the tip size of the NW was reduced and NWs with a tip size of 20 nm were successfully formed. Subsequently, a thin InAsP layer was grown on the annealed NWs and their photoluminescence was investigated at low temperatures. The characterization results indicated the formation of InAsP quantum dots (QDs) emitting in the telecom band. Our approach is useful for reducing the size of the NWs and for the controlled formation of InAsP QDs embedded in InP NWs in photonic devices compatible with telecom bands.

Selective-Area Growth of Vertical InGaAs/GaSb Core-Shell Nanowires on Silicon and Dual Switching Properties.

The epitaxy of the Sb-related quantum well structure has been extensively investigated. However, the GaSb facet growth in selective-area growth (SAG) and GaSb nanostructures has not been investigated because of the surface diffusion complexity and surfactant effect of Sb adatoms. Here, the growth morphology of GaSb structures in SAG was characterized via InGaAs nanowires (NWs) monolithically grown on a Si template. SAG of GaSb using NWs included four growth processes: lateral-over growth along the ⟨1̅10⟩ directions, axial growth along the vertical ⟨111⟩ B direction, downward step-flow growth, and desorption of Sb adatoms from the NW sidewalls. The dominant processes could be controlled by the GaSb growth temperature and could form smooth GaSb shell layers. The vertical diode of InGaAs/GaSb core-shell NWs on Si exhibited moderate rectifying properties because of the InGaAs/GaSb heterojunction band alignment. In the vertical transistor application, specific dual-carrier modulation behaviors, such as p-channel field-effect transistor and n-channel tunnel field-effect transistor modes, occurred in the same transistor architecture. This was because the carrier transport changed with respect to the bias polarity. This specific transistor behavior in the InGaAs/GaSb core-shell NW on Si would expand possibilities for integrated circuit technologies using only a single transistor structure.

Creation of unexplored tunnel junction by heterogeneous integration of InGaAs nanowires on germanium.

Heteroepitaxy has inherent concerns regarding crystal defects originated from differences in lattice constant, thermal expansion coefficient, and crystal structure. The selection of III-V materials on group IV materials that can avoid these issues has however been limited for applications such as photonics, electronics, and photovoltaics. Here, we studied nanometer-scale direct integration of InGaAs nanowires (NWs) on Ge in terms of heterogenous integration and creation of functional materials with an as yet unexplored heterostructure. We revealed that changing the initial Ge into a (111)B-polar surce anabled vertical InGaAs NWs to be integrated for all In compositions examined. Moreover, the growth naturally formed a tunnel junction across the InGaAs/Ge interface that showed a rectification property with a huge current density of several kAcm-2 and negative differential resistance with a peak-to-valley current ratio of 2.8. The described approach expands the range of material combinations for high-performance transistors, tandem solar cells, and three-dimensional integrations.

Demonstration of InP/InAsP/InP axial heterostructure nanowire array vertical LEDs.

Semiconductor nanowires (NWs), which have nanoscale footprints, enable us to realize various quantum structures with excellent position and size controllability, utilizing a wide range of materials for heterostructures. In addition, enhancing light extraction and controlling spontaneous emission by modifying their size and shape are possible. Thus, NWs are promising materials for nanoscale light sources applicable from visible to telecommunication bands. In this study, we grew InP/InAsP/InP axial heterostructure NWs, where the InAsP layer was embedded to serve as an active layer, by selective-area growth and demonstrated vertical NW array light-emitting diodes (LEDs) as a step towards realizing on-demand single photon sources. The NW array LEDs showed rectifying characteristics and electroluminescence originating from the embedded InAsP layer in the near-infrared region.

Rational synthesis of atomically thin quantum structures in nanowires based on nucleation processes.

Excitonic properties in quantum dot (QD) structure are essential properties for applications in quantum computing, cryptography, and photonics. Top-down fabrication and bottom-up growth by self-assembling for forming the QDs have shown their usefulness. These methods, however, still inherent issues in precision integrating the regimes with high reproducibility and positioning to realize the applications with on-demand quantum properties on Si platforms. Here, we report on a rational synthesis of embedding atomically thin InAs in nanowire materials on Si by selective-area regrowth. An extremely slow growth rate specified for the synthesis demonstrated to form smallest quantum structures reaching nuclear size, and provided good controllability for the excitonic states on Si platforms. The system exhibited sharp photoluminescence spectra originating from exciton and bi-exciton suggesting the carriers were confined inside the nuclei. The selective-area regrowth would open new approach to integrate the exciton states with Si platforms as building-blocks for versatile quantum systems.

Characterization of nanowire light-emitting diodes grown by selective-area metal-organic vapor-phase epitaxy.

We report a systematic study on the current injection and radiative carrier recombination in InP nanowire (NW) light-emitting diodes (LEDs). The InP NWs with axial p-n structures, grown by selective-area metal organic vapor-phase epitaxy, had mixed crystal structures between those of zincblende and wurtzite, mainly in the p-regions. The temperature dependence of the current-voltage (I-V), electroluminescence (EL), and current-light output (I-L) characteristics was investigated. The temperature dependence of the I-V characteristics revealed that tunneling was the main mechanism of carrier transport through the p-n junction in the present NW-LEDs. The temperature and bias voltage dependences of EL showed a complex but systematic behavior, where peaks exhibiting bias-dependent and independent energy positions coexisted and the relative intensity showed a transition with increasing temperature. The external quantum efficiency showed a droop at low temperatures, indicating a reduced injection efficiency at low temperatures. These observations were explained by the radiative and nonradiative tunneling, and suggested a strong effect of the nonradiative tunneling at low temperatures.

Growth of All-Wurtzite InP/AlInP Core-Multishell Nanowire Array.

We demonstrated the formation of all-wurtzite (WZ) InP/AlInP core-multishell (CMS) nanowires (NWs) by selective-area growth with the crystal structure transfer method. The CMS NWs consisting of an AlInP-based double heterostructure showed that the crystal structure of the multishell succeeded to the WZ phase from the WZ InP NW by the crystal structure transfer method. Transmission electron microscopy revealed that the core-shell interface had a few stacking faults due to lattice mismatch. In addition, lattice constants of WZ AlInP with a variation of Al content were determined by X-ray diffraction reciprocal space mappings, and the WZ AlInP shell had tensile strain along the c-axis. The WZ AlInP shells (Al content: 25-54%) showed cathode luminescence emissions at 1.6-2.1 eV, possibly related to In-rich domains due to composition fluctuation in the WZ AlInP shell.

Selective-Area Growth of InAs Nanowires on Ge and Vertical Transistor Application.

III-V compound semiconductor and Ge are promising channel materials for future low-power and high-performance integrated circuits. A heterogeneous integration of these materials on the same platform, however, raises serious problem owing to a huge mismatch of carrier mobility. We proposed direct integration of perfectly vertically aligned InAs nanowires on Ge as a method for new alternative integrated circuits and demonstrated a high-performance InAs nanowire-vertical surrounding-gate transistor. Virtually 100% yield of vertically aligned InAs nanowires was achieved by controlling the initial surface of Ge and high-quality InAs nanowires were obtained regardless of lattice mismatch (6.7%). The transistor performance showed significantly higher conductivity with good gate control compared to Si-based conventional field-effect transistors: the drain current was 0.65 mA/µm, and the transconductance was 2.2 mS/µm at drain-source voltage of 0.50 V. These demonstrations are a first step for building alternative integrated circuits using vertical III-V/multigate planar Ge FETs.

Sub 60 mV/decade switch using an InAs nanowire-Si heterojunction and turn-on voltage shift with a pulsed doping technique.

We report changes of turn-on voltage in InAs-Si heterojunction steep subthreshold-slope transistors by the Zn-pulsed doping technique for InAs nanowire channels. The doping of the nanowire channel moderately changes turn-on voltage from negative to positive voltage, while keeping a steep subthreshold-slope of 30 mV/decade under reverse bias direction. The formation of pseudointrinsic InAs segment is found to be important to make a normally off transistor with a steep subthreshold slope.

GaAs nanowire growth on polycrystalline silicon thin films using selective-area MOVPE.

The growth mechanism of GaAs nanowires (NWs) grown on polycrystalline silicon (poly-Si) thin films using selective-area metalorganic vapor-phase epitaxy was investigated. Wire structures were selectively grown in the mask openings on a poly-Si substrate. The appearance ratio of wire structures strongly depended on the growth conditions and deposition temperature of the poly-Si substrate. Evaluation of the grown shapes and growth characteristics revealed that GaAs NWs grown on a poly-Si substrate have the same growth mechanism as conventional GaAs NWs grown on a single-crystalline GaAs or Si substrate. Experiments showed that the wire structure yield can be improved by increasing the Si grain size and/or increasing the Si deposition temperature. The growth model proposed for understanding NW growth on poly-Si is based on the mask opening size, the Si grain size, and the growth conditions. The ability to control the growth mode is promising for the formation of NWs with complex structures on poly-Si thin layers.

A III-V nanowire channel on silicon for high-performance vertical transistors.

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Bidirectional growth of indium phosphide nanowires.

We present a bidirectional growth mode of InP nanowires grown by selective-area metalorganic vapor-phase epitaxy (SA-MOVPE). We studied the effect of the supply ratio of DEZn ([DEZn]) on InP grown structure morphology and crystal structures during the SA-MOVPE. Two growth regimes were observed in the investigated range of the [DEZn] on an InP(111)B substrate. At low [DEZn], grown structures formed tripod structures featuring three nanowires branched toward the [111]A directions. At high [DEZn], we obtained hexagonal pillar-type structures vertically grown on the (111)B substrate. These results show that the growth direction changes from [111]A to [111]B as [DEZn] is increased. We propose a growth mechanism based on the correlation between the incident facet of rotational twins and the shapes of the grown structures. Our results bring us one step closer to controlling the direction of nanowires on a Si substrate that has a nonpolar nature. They can also be applied to the development of InP nanowire devices.

Position-controlled III-V compound semiconductor nanowire solar cells by selective-area metal-organic vapor phase epitaxy.

We demonstrate position-controlled III-V semiconductor nanowires (NWs) by using selective-area metal-organic vapor phase epitaxy and their application to solar cells. Efficiency of 4.23% is achieved for InP core-shell NW solar cells. We form a 'flexible NW array' without a substrate, which has the advantage of saving natural resources over conventional thin film photovoltaic devices. Four junction NW solar cells with over 50% efficiency are proposed and discussed.

Zinc blende and wurtzite crystal phase mixing and transition in indium phosphide nanowires.

Indium phosphide (InP) nanowires, which have crystal phase mixing and transition from zinc blende (ZB) to wurtzite (WZ), are grown in intermediate growth conditions between ZB and WZ by using selective-area metalorganic vapor phase epitaxy (SA-MOVPE). The shape of InP nanowires is tapered unlike ZB or WZ nanowires. A growth model has been developed for the tapered nanowires, which is simply described as the relationship between tapered angle and the ratio of ZB and WZ segments. In addition, the peak energy shift in photoluminescence measurement was attributed to the quantum confinement effect of the quantum well of the ZB region located in the polytypic structure of ZB and WZ in nanowires.

Structural transition in indium phosphide nanowires.

We study the catalyst-free growth of InP nanowires using selective-area metalorganic vapor phase epitaxy (SA-MOVPE) and show that they undergo transition of crystal structures depending on the growth conditions. InP nanowires were grown on InP substrates where the mask for the template of the growth was defined. The nanowires were grown only in the opening region of the mask. It was found that uniform array of InP nanowires with hexagonal cross section and with negligible tapering were grown under two distinctive growth conditions. The nanowires grown in two different growth conditions were found to exhibit different crystal structures. It was also found that the orientation and size of hexagon were different, suggesting that the difference of the growth behavior. A model for the transition of crystal structure is presented based on the atomic arrangements and termination of InP surfaces. Photoluminescence measurement revealed that the transition took place for nanowires with diameters up to 1 microm.

GaAs/AlGaAs core multishell nanowire-based light-emitting diodes on Si.

We report on integration of GaAs nanowire-based light-emitting-diodes (NW-LEDs) on Si substrate by selective-area metalorganic vapor phase epitaxy. The vertically aligned GaAs/AlGaAs core-multishell nanowires with radial p-n junction and NW-LED array were directly fabricated on Si. The threshold current for electroluminescence (EL) was 0.5 mA (current density was approximately 0.4 A/cm(2)), and the EL intensity superlinearly increased with increasing current injections indicating superluminescence behavior. The technology described in this letter could help open new possibilities for monolithic- and on-chip integration of III-V NWs on Si.

Selective-area growth of vertically aligned GaAs and GaAs/AlGaAs core-shell nanowires on Si(111) substrate.

We report on selective-area growth of vertically aligned GaAs nanowires on Si(111) substrate. Modification of the initial Si(111) surface by pretreatment under an AsH(3) atmosphere and low-temperature growth of GaAs were important for controlling the growth orientations of the GaAs nanowire on the Si(111) surface. We also found that the size of openings strongly affected the growth morphology of GaAs nanowires on Si(111). Small diameter openings reduced the antiphase defects and improved the optical properties in the GaAs nanowires. Moreover, we realized coherent growth without misfit dislocation at the GaAs/Si interface. Finally, we demonstrated fabrication of a GaAs/AlGaAs core-shell nanowire array on a Si surface and revealed that the luminescence intensity was markedly enhanced by passivation effects. These results are promising for future III-V nanowire-based optoelectronic integration on Si platforms.

Control of InAs nanowire growth directions on Si.

We report on control of growth directions of InAs nanowires on Si substrate. We achieved to integrate vertical InAs nanowires on Si by modifying initial Si(111) surface in selective-area metal-organic vapor phase epitaxy with flow-rate modulation mode at low temperature. Cross-sectional transmission electron microscope and Raman scattering showed that misfit dislocation with local strains were accommodated in the interface.