Effect of interface defects on electrical characteristics of a-ITGZO TFTs under bottom, top, and dual gatings.

Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm2/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.6 cm2/V∙s, 301 mV/decade) and bottom (11.1 cm2/V∙s, 487 mV/decade) gatings. For an a-ITGZO TFT, oxygen deficiencies are more prevalent in the bottom-gate dielectric interface than in the top-gate dielectric interface, and they are less prevalent inside the channel layer than at the interfaces, indicating that the presence of oxygen deficiencies significantly affects the field-effect mobility and subthreshold swing. Moreover, the variation in the electrical characteristics due to the positive bias stress is discussed here.

J-MISFET Hybrid Dual-Gate Switching Device for Multifunctional Optoelectronic Logic Gate Applications.

High-performance and low operating voltage are becoming increasingly significant device parameters to meet the needs of future integrated circuit (IC) processors and ensure their energy-efficient use in upcoming mobile devices. In this study, we suggest a hybrid dual-gate switching device consisting of the vertically stacked junction and metal-insulator-semiconductor (MIS) gate structure, named J-MISFET. It shows excellent device performances of low operating voltage (<0.5 V), drain current ON/OFF ratio (∼4.7 × 105), negligible hysteresis window (<0.5 mV), and near-ideal subthreshold slope (SS) (60 mV/dec), making it suitable for low-power switching operation. Furthermore, we investigated the switchable NAND/NOR logic gate operations and the photoresponse characteristics of the J-MISFET under the small supply voltage (0.5 V). To advance the applications further, we successfully demonstrated an integrated optoelectronic security logic system comprising 2-electric inputs (for encrypted data) and 1-photonic input signal (for password key) as a hardware security device for data protection. Thus, we believe that our J-MISFET, with its heterogeneous hybrid gate structures, will illuminate the path toward future device configurations for next-generation low-power electronics and multifunctional security logic systems in a data-driven society.

Enhanced BSA Detection Precision: Leveraging High-Performance Dual-Gate Ion-Sensitive Field-Effect-Transistor Scheme and Surface-Treated Sensing Membranes.

Bovine serum albumin (BSA) is commonly incorporated in vaccines to improve stability. However, owing to potential allergic reactions in humans, the World Health Organization (WHO) mandates strict adherence to a BSA limit (≤50 ng/vaccine). BSA detection with conventional techniques is time-consuming and requires specialized equipment. Efficient alternatives such as the ion-sensitive field-effect transistor (ISFET), despite rapid detection, affordability, and portability, do not detect BSA at low concentrations because of inherent sensitivity limitations. This study proposes a silicon-on-insulator (SOI) substrate-based dual-gate (DG) ISFET platform to overcome these limitations. The capacitive coupling DG structure significantly enhances sensitivity without requiring external circuits, owing to its inherent amplification effect. The extended-gate (EG) structure separates the transducer unit for electrical signal processing from the sensing unit for biological detection, preventing chemical damage to the transducer, accommodating a variety of biological analytes, and affording easy replaceability. Vapor-phase surface treatment with (3-Aminopropyl) triethoxysilane (APTES) and the incorporation of a SnO2 sensing membrane ensure high BSA detection efficiency and sensitivity (144.19 mV/log [BSA]). This DG-FET-based biosensor possesses a simple structure and detects BSA at low concentrations rapidly. Envisioned as an effective on-site diagnostic tool for various analytes including BSA, this platform addresses prior limitations in biosensing and shows promise for practical applications.

Reliable measurement methods for the isovolumic relaxation time: comparisons of dual gate Doppler and seven other methods.

PURPOSE: Isovolumic relaxation time (IVRT) is a useful indicator of diastolic dysfunction. However, a measurement method for IVRT has not been established. The Dual Gate Doppler method, which can record two separate pulse-wave Doppler signals simultaneously using two sample gates, may be ideal for measuring IVRT. This study aimed to evaluate the accuracy of IVRT measured using conventional methods versus that measured using the Dual Gate Doppler method. METHODS: A total of 104 patients (mean age 58 ± 21 years, 48 women) were examined using ultrasound equipment with Dual Gate Doppler at our hospital. In addition to Dual Gate Doppler method, IVRTs were measured using seven different methods: pulsed Doppler (PW method), continuous wave Doppler (CW method), and other methods. The IVRT values obtained using the Dual Gate Doppler method were compared with those measured using other methods. RESULTS: All IVRTs measured using conventional methods showed a strong correlation with the that measured using the Dual Gate Doppler method. However, there were slight deifferences among the IVRTs depending on the method. The PW method and the PW time difference method using only the PW showed small statistical bias and were not complicated. The IVRT measured using the CW method was significantly longer than that measured using the Dual Gate Doppler method. CONCLUSIONS: Among the conventional methods, the PW method was the simplest and most practical method for measuring the IVRT in any conditions as arrhythmias. It is important to recognize the characteristics of IVRTs based on the measurement method.

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping.

The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks in which desired junction is formed by van der Waals (vdW) integration and selective oxygen plasma-doping into spacer regions. The exceptional electrostatic controllability with a high on/off current ratio and small subthreshold swing (SS) of plasma doped p-FETs is achieved with the self-aligned metal/hBN gate stacks. To demonstrate the effectiveness of our approach, we construct a PMOS inverter using this device architecture, which exhibits a remarkably low power consumption of approximately 4.5 nW.

The Influence of Special Environments on SiC MOSFETs.

In this work, the influences of special environments (hydrogen gas and high temperature, high humidity environments) on the performance of three types of SiC MOSFETs are investigated. The results reveal several noteworthy observations. Firstly, after 500 h in a hydrogen gas environment, all the SiC MOSFETs exhibited a negative drift in threshold voltage, accompanied by an increase in maximum transconductance and drain current (@ VGS/VDS = 13 V/3 V). This phenomenon can be attributed to that the hydrogen atoms can increase the positive fixed charges in the oxide and increase the electron mobility in the channel. In addition, high temperature did not intensify the impact of hydrogen on the devices and electron mobility. Instead, prolonged exposure to high temperatures may induce stress on the SiO2/SiC interface, leading to a decrease in electron mobility, subsequently reducing the transconductance and drain current (@ VGS/VDS = 13 V/3 V). The high temperature, high humidity environment can cause a certain negative drift in the devices' threshold voltage. With the increasing duration of the experiment, the maximum transconductance and drain current (@ VGS/VDS = 18V (20 V)/3 V) gradually decreased. This may be because the presence of moisture can lead to corrosion of the devices' metal contacts and interconnects, which can increase the devices' resistance and lead to a decrease in the devices' maximum transconductance and drain current.

Rapid and simultaneous multiple detection of a tripledemic using a dual-gate oxide semiconductor thin-film transistor-based immunosensor.

The simultaneous infection with a tripledemic-simultaneous infection with influenza A pH1N1 virus (Flu), severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2), and respiratory syncytial virus (RSV)-necessitates the development of accurate and fast multiplex diagnostic tests. The coronavirus disease 2019 (COVID-19) pandemic has emphasized the importance of virus detection. Field-effect transistor (FET)-based immuno-biosensors have a short detection time and do not require labeling or polymerase chain reaction. This study demonstrates the rapid, sensitive detection of influenza A pH1N1, SARS-CoV-2, and RSV using a multiplex immunosensor based on a dual-gate oxide semiconductor thin-film transistor (TFT), a type of FET. The dual-gate oxide TFT was modified by adjusting both top and bottom gate insulators to improve capacitive coupling to approximately 120-fold amplification, exhibiting a high pH sensitivity of about 10 V/pH. The dual-gate oxide TFT-based immunosensor detected the target proteins (hemagglutinin (HA) protein of Flu, spike 1 (S1) protein of SARS-CoV-2, and fusion protein of RSV) of each virus, with a limit of detection of approximately 1 fg/mL. Cultured viruses in phosphate-buffered saline or artificial saliva and clinical nasopharynx samples were detected in 1-µL sample volumes within 60 s. This promising diagnosis could be potentially as point-of-care tests to facilitate a prompt response to future pandemics with high sensitivity and multiplexed detection without pretreatment.

Influence of Gate Geometry on the Characteristics of AlGaN/GaN Nanochannel HEMTs for High-Linearity Applications.

In this study, AlGaN/GaN nanochannel high-electron-mobility transistors (HEMTs) with tri-gate (TGN-devices) and dual-gate (DGN-devices) structures were fabricated and investigated. It was found that the peak value of the transconductance (Gm), current gain cut-off frequency (fT) and power gain cut-off frequency (fmax) of the TGN-devices were larger than that of the DGN-devices because of the enhanced gate control from the top gate. Although the TGN-devices and DGN-devices demonstrated flattened transconductance, fT and fmax profiles, the first and second transconductance derivatives of the DGN-devices were lower than those of the TGN-devices, implying an improvement in linearity. With the nanochannel width decreased, the peak value of the transconductance and the first and second transconductance derivatives increased, implying the predominant influence of sidewall gate capacitance on the transconductance and linearity. The comparison of gate capacitance for the TGN-devices and DGN-devices revealed that the gate capacitance of the tri-gate structure was not simply a linear superposition of the top planar gate capacitance and sidewall gate capacitance of the dual-gate structure, which could be attributed to the difference in the depletion region shape for tri-gate and dual-gate structures.

Reconfigurable Logic-in-Memory Constructed Using an Organic Antiambipolar Transistor.

We demonstrate an electrically reconfigurable two-input logic-in-memory (LIM) using a dual-gate-type organic antiambipolar transistor (DG-OAAT). The attractive feature of this device is that a phthalocyanine-cored star-shaped polystyrene is used as a nano-floating gate, which enables the electrical switching of individual logic circuits and stores the circuit information by the nonvolatile memory effect. First, the DG-OAAT exhibited Λ-shaped transfer curves with hysteresis by sweeping the bottom-gate voltage. Programming and erasing operations enabled the reversible shift of the Λ-shaped transfer curves. Furthermore, the top-gate voltage effectively tuned the peak voltages of the transfer curves. Consequently, the combination of dual-gate and memory effects achieved electrically reconfigurable two-input LIM operations. Individual logic circuits (e.g., OR/NAND, XOR/NOR, and AND/XOR) were reconfigured by the corresponding programming and erasing operations without any variations in the input signals. Our device concept has the potential to fulfill an epoch-making organic integration circuit with a simple device configuration.

Pushing the Limits of Biosensing: Selective Calcium Ion Detection with High Sensitivity via High-k Gate Dielectric Engineered Si Nanowire Random Network Channel Dual-Gate Field-Effect Transistors.

Calcium ions (Ca2+) are abundantly present in the human body; they perform essential roles in various biological functions. In this study, we propose a highly sensitive and selective biosensor platform for Ca2+ detection, which comprises a dual-gate (DG) field-effect transistor (FET) with a high-k engineered gate dielectric, silicon nanowire (SiNW) random network channel, and Ca2+-selective extended gate. The SiNW channel device, which was fabricated via the template transfer method, exhibits superior Ca2+ sensing characteristics compared to conventional film channel devices. An exceptionally high Ca2+ sensitivity of 208.25 mV/dec was achieved through the self-amplification of capacitively coupled DG operation and an enhanced amplification ratio resulting from the high surface-to-volume ratio of the SiNW channel. The SiNW channel device demonstrated stable and reliable sensing characteristics, as evidenced by minimal hysteresis and drift effects, with the hysteresis voltage and drift rate measuring less than 6.53% of the Ca2+ sensitivity. Furthermore, the Ca2+-selective characteristics of the biosensor platform were elucidated through experiments with pH buffer, NaCl, and KCl solutions, wherein the sensitivities of the interfering ions were below 7.82% compared to the Ca2+ sensitivity. The proposed Ca2+-selective biosensor platform exhibits exceptional performance and holds great potential in various biosensing fields.

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley-Read-Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.

Dual-Gate Organic Thin-Film Transistor and Multiplexer Chips for the Next Generation of Flexible EG-ISFET Sensor Chips.

Ion-sensitive field-effect transistors (ISFETs) are used as elementary devices to build many types of chemical sensors and biosensors. Organic thin-film transistor (OTFT) ISFETs use either small molecules or polymers as semiconductors together with an additive manufacturing process of much lower cost than standard silicon sensors and have the additional advantage of being environmentally friendly. OTFT ISFETs' drawbacks include limited sensitivity and higher variability. In this paper, we propose a novel design technique for integrating extended-gate OTFT ISFETs (OTFT EG-ISFETs) together with dual-gate OTFT multiplexers (MUXs) made in the same process. The achieved results show that our OTFT ISFET sensors are of the state of the art of the literature. Our microsystem architecture enables switching between the different ISFETs implemented in the chip. In the case of sensors with the same gain, we have a fault-tolerant architecture since we are able to replace the faulty sensor with a fault-free one on the chip. For a chip including sensors with different gains, an external processor can select the sensor with the required sensitivity.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

High-Performance FET-Based Dopamine-Sensitive Biosensor Platform Based on SOI Substrate.

Dopamine is a catecholamine neurotransmitter that plays a significant role in the human central nervous system, even at extremely low concentrations. Several studies have focused on rapid and accurate detection of dopamine levels using field-effect transistor (FET)-based sensors. However, conventional approaches have poor dopamine sensitivity with values <11 mV/log [DA]. Hence, it is necessary to increase the sensitivity of FET-based dopamine sensors. In the present study, we proposed a high-performance dopamine-sensitive biosensor platform based on dual-gate FET on a silicon-on-insulator substrate. This proposed biosensor overcame the limitations of conventional approaches. The biosensor platform consisted of a dual-gate FET transducer unit and a dopamine-sensitive extended gate sensing unit. The capacitive coupling between the top- and bottom-gate of the transducer unit allowed for self-amplification of the dopamine sensitivity, resulting in an increased sensitivity of 373.98 mV/log[DA] from concentrations 10 fM to 1 µM. Therefore, the proposed FET-based dopamine sensor is expected to be widely applied as a highly sensitive and reliable biosensor platform, enabling fast and accurate detection of dopamine levels in various applications such as medical diagnosis and drug development.

Modulation of Contact Resistance of Dual-Gated MoS2 FETs Using Fermi-Level Pinning-Free Antimony Semi-Metal Contacts.

Achieving low contact resistance (RC ) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS2 devices are systematically analyzed as a function of top and bottom gate-voltages (VTG and VBG ). The semimetal contacts not only significantly reduce RC but also induce a strong dependence of RC on VTG , in sharp contrast to Ti contacts that only modulate RC by varying VBG . The anomalous behavior is attributed to the strongly modulated pseudo-junction resistance (Rjun ) by VTG , resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by VTG as metal screens the electric field from the applied VTG . Technology computer aided design simulations further confirm the contribution of VTG to Rjun , which improves overall RC of Sb-contacted MoS2 devices. Consequently, the Sb contact has a distinctive merit in dual-gated (DG) device structure, as it greatly reduces RC and enables effective gate control by both VBG and VTG . The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals.

Heterogeneous CMOS Integration of InGaAs-OI nMOSFETs and Ge pMOSFETs Based on Dual-Gate Oxide Technique.

A compatible fabrication technology for integrating InGaAs nMOSFETs and Ge pMOSFETs is developed based on the development of the two-step gate oxide fabrication strategy. The direct wafer bonding method was utilized to obtain the InGaAs-Insulator-Ge structure, providing the heterogeneous channels for CMOS integration. Superior transistor characteristics were achieved by optimizing the InGaAs gate oxide with a self-cleaning process in atomic layer deposition, and modifying the Ge gate oxide by the ozone post oxidation (OPO) technique, in the sequential two-step gate oxide fabrication process. With the combination of the gate-first fabrication process, superior on- and off-state characteristics, i.e., on current up to 8.3 µA/µm and leakage as low as 10-6 µA/µm, have been demonstrated in the integrated MOSFETs, together with the preferable symmetric output characteristics that promises excellent CMOS performances.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 µA/µm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Electrically Reconfigurable Organic Logic Gates: A Promising Perspective on a Dual-Gate Antiambipolar Transistor.

Electrically reconfigurable organic logic circuits are promising candidates for realizing new computation architectures, such as artificial intelligence and neuromorphic devices. In this study, multiple logic gate operations are attained based on a dual-gate organic antiambipolar transistor (DG-OAAT). The transistor exhibits a Λ-shaped transfer curve, namely, a negative differential transconductance at room temperature. It is important to note that the peak voltage of the drain current is precisely tuned by three input signals: bottom-gate, top-gate, and drain voltages. This distinctive feature enables multiple logic gate operations with "only a single DG-OAAT," which are not obtainable in conventional transistors. Five logic gate operations, which correspond to AND, OR, NAND, NOR, and XOR, are demonstrated by adjusting the bottom-gate and top-gate voltages. Moreover, varying the drain voltage makes it possible to reversibly switch two logic gates, e.g., NAND/NOR and OR/XOR. In addition, the DG-OAATs show a high degree of stability and reliability. The logic gate operations are observed even months later. The hysteresis in the transfer curves is also negligible. Thus, the device concept is promising for realizing multifunctional logic circuits with a simple transistor configuration. Hence, these findings are expected to surpass the current limitations in complementary metal-oxide-semiconductor devices.

Dual-Ferroelectric-Coupling-Engineered Two-Dimensional Transistors for Multifunctional In-Memory Computing.

In-memory computing featuring a radical departure from the von Neumann architecture is promising to substantially reduce the energy and time consumption for data-intensive computation. With the increasing challenges facing silicon complementary metal-oxide-semiconductor (CMOS) technology, developing in-memory computing hardware would require a different platform to deliver significantly enhanced functionalities at the material and device level. Here, we explore a dual-gate two-dimensional ferroelectric field-effect transistor (2D FeFET) as a basic device to form both nonvolatile logic gates and artificial synapses, addressing in-memory computing simultaneously in digital and analog spaces. Through diversifying the electrostatic behaviors in 2D transistors with the dual-ferroelectric-coupling effect, rich logic functionalities including linear (AND, OR) and nonlinear (XNOR) gates were obtained in unipolar (MoS2) and ambipolar (MoTe2) FeFETs. Combining both types of 2D FeFETs in a heterogeneous platform, an important computation circuit, i.e., a half-adder, was successfully constructed with an area-efficient two-transistor structure. Furthermore, with the same device structure, several key synaptic functions are shown at the device level, and an artificial neural network is simulated at the system level, manifesting its potential for neuromorphic computing. These findings highlight the prospects of dual-gate 2D FeFETs for the development of multifunctional in-memory computing hardware capable of both digital and analog computation.

Comparison between conventional duplex ultrasonography and the dual-gate Doppler mode for hemodynamic measurements of the carotid arteries.

PURPOSE: This study investigated the correlations of hemodynamic parameters measured to quantify stenosis between the gold-standard duplex ultrasonography and the dual-gate Doppler mode. METHODS: Patients examined due to suspicion of carotid artery stenosis or for surveillance of known stenosis were invited to participate in this prospective single-center study. Upon acceptance, the hemodynamic characteristics of the carotid arteries were determined successively in standard duplex and dual-gate Doppler modes. The correlations between the two modes were analyzed by computing Pearson coefficients (r2) and Lin concordance coefficients (ρc). The degree of agreement between the two methods was visualized using Bland-Altman graphical representations. RESULTS: The correlation between internal carotid artery peak systolic velocity measured by standard duplex ultrasonography and dual-gate Doppler mode was good (r2=0.642). The same high level of correlation was observed for the carotid ratio (r2=0.544). However, the Bland-Altman graphical representation and the Lin concordance coefficients (ρc=0.75 and ρc=0.74 for the internal carotid artery peak systolic velocity and carotid ratio, respectively) showed that a lack of precision generated some discrepancies between the two measurement methods. CONCLUSION: Although some discrepancies were observed, the hemodynamic measurements were closely correlated between the two ultrasonography modes. Therefore, the dual-gate Doppler mode may have obvious advantages over conventional ultrasonography, offering interesting development possibilities.