Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration.

Ferroelectric field-effect transistors (FeFETs) are increasingly important for in-memory computing and monolithic 3D (M3D) integration in system-on-chip (SoC) applications. However, the high-temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia-based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle > 106, retention > 106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7 V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µC cm-2) and pattern recognition rate-based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin-film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

Epitaxial Growth of Large-Scale 2D CrTe2 Films on Amorphous Silicon Wafers With Low Thermal Budget.

2D van der Waals (vdW) magnets open landmark horizons in the development of innovative spintronic device architectures. However, their fabrication with large scale poses challenges due to high synthesis temperatures (>500 °C) and difficulties in integrating them with standard complementary metal-oxide semiconductor (CMOS) technology on amorphous substrates such as silicon oxide (SiO2) and silicon nitride (SiNx). Here, a seeded growth technique for crystallizing CrTe2 films on amorphous SiNx/Si and SiO2/Si substrates with a low thermal budget is presented. This fabrication process optimizes large-scale, granular atomic layers on amorphous substrates, yielding a substantial coercivity of 11.5 kilo-oersted, attributed to weak intergranular exchange coupling. Field-driven Néel-type stripe domain dynamics explain the amplified coercivity. Moreover, the granular CrTe2 devices on Si wafers display significantly enhanced magnetoresistance, more than doubling that of single-crystalline counterparts. Current-assisted magnetization switching, enabled by a substantial spin-orbit torque with a large spin Hall angle (85) and spin Hall conductivity (1.02 × 107 ℏ/2e Ω⁻¹ m⁻¹), is also demonstrated. These observations underscore the proficiency in manipulating crystallinity within integrated 2D magnetic films on Si wafers, paving the way for large-scale batch manufacturing of practical magnetoelectronic and spintronic devices, heralding a new era of technological innovation.

Formation techniques for upper active channel in monolithic 3D integration: an overview.

The concept of three-dimensional stacking of device layers has attracted significant attention with the increasing difficulty in scaling down devices. Monolithic 3D (M3D) integration provides a notable benefit in achieving a higher connection density between upper and lower device layers than through-via-silicon. Nevertheless, the practical implementation of M3D integration into commercial production faces several technological challenges. Developing an upper active channel layer for device fabrication is the primary challenge in M3D integration. The difficulty arises from the thermal budget limitation for the upper channel process because a high thermal budget process may degrade the device layers below. This paper provides an overview of the potential technologies for forming active channel layers in the upper device layers of M3D integration, particularly for complementary metal-oxide-semiconductor devices and digital circuits. Techniques are for polysilicon, single crystal silicon, and alternative channels, which can solve the temperature issue for the top layer process.

MoS2 as an Effective Cu Diffusion Barrier with a Back-End Compatible Process.

This study demonstrates molybdenum disulfide (MoS2) as a superior candidate as a diffusion barrier and liner. This research explores a newly developed process to show how effectively MoS2 can be applied. First, a new approach is developed to prepare molybdenum disulfide (MoS2) by microwave plasma-enhanced sulfurization (MW-PES). MW-PES can rapidly and directly grow on the target substrate at low temperatures, which is compatible with the back-end-of-line (BEOL) technology. Second, the performance of MW-PES MoS2 as a diffusion barrier and liner is reported in the subsequent section. Through time-dependent dielectric breakdown (TDDB) measurements, MoS2 is shown to have a barrier property better than that of the current material, Ta, with the same thickness. According to the model fitting, the lifetime of the device is about 45.2 times the lifetime under normal operating conditions. Furthermore, MoS2 shows its superior thermal stability in maintaining the barrier properties. MoS2 is proven to be an excellent interface as a liner as it can provide sufficient adhesion and wettability to further effectively reduce the surface scattering of copper (Cu) and significantly lower the circuit resistance.

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs.

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits.

Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼106) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration. A 1-trit ternary full adder designed with this AAS device exhibits excellent power-delay product performance (∼122 aJ) with extremely low power (∼0.15 µW, 7 times lower than the reference circuit) and lower device count than those of other ternary device candidates.

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration.

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 µA/µm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 µA/µm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 µW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.

Low Thermal Budget Heteroepitaxial Gallium Oxide Thin Films Enabled by Atomic Layer Deposition.

This work explores the applicability of atomic layer deposition (ALD) in producing highly oriented crystalline gallium oxide films on foreign substrates at low thermal budgets. The effects of substrate, deposition temperature, and annealing process on formation of crystalline gallium oxide are discussed. The Ga2O3 films exhibited a strong preferred orientation on the c-plane sapphire substrate. The onset of formation of crystalline gallium oxide is determined, at which only two sets of planes, i.e., α-Ga2O3 (006) and ß-Ga2O3 (4̅02), are present parallel to the surface. More specifically, this work reports, for the first time, that epitaxial gallium oxide films on sapphire start to form at deposition temperatures ≥ 190 °C by using an optimized plasma-enhanced ALD process such that α-Ga2O3 (006)∥α-Al2O3 (006) and ß-Ga2O3 (2̅01)∥α-Al2O3 (006). Both α-Ga2O3 (006) and ß-Ga2O3 (2̅01) planes are polar planes (i.e., consisting of only one type of atom, either Ga or O) and, therefore, favorable to form by ALD at such low deposition temperatures. Ellipsometry and van der Pauw measurements confirmed that the crystalline films have optical and electrical properties close to bulk gallium oxide. The film grown at 277 °C was determined to have superior properties among as-deposited films. Using TEM to locate α-Ga2O3 and ß-Ga2O3 domains in the as-deposited crystalline films, we proposed a short annealing scheme to limit the development of α-Ga2O3 domains in the film and produce pure ß-Ga2O3 films via an energy-efficient process. A pure ß-Ga2O3 phase on sapphire with ß-Ga2O3 (2̅01)∥α-Al2O3 (006) was successfully achieved by using the proposed process at the low annealing temperature of 550 °C preceded by the low deposition temperature of 190 °C. The results of this work enable epitaxial growth of gallium oxide thin films, with superior material properties offered by ALD, not only with potential applications as a high-performance material in reducing global energy consumption but also with an energy-efficient fabrication process.

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits.

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

A Comprehensive Study on the Effect of TiN Top and Bottom Electrodes on Atomic Layer Deposited Ferroelectric Hf0.5Zr0.5O2 Thin Films.

The discovery of ferroelectricity in HfO2-based materials in 2011 provided new research directions and opportunities. In particular, for atomic layer deposited Hf0.5Zr0.5O2 (HZO) films, it is possible to obtain homogenous thin films with satisfactory ferroelectric properties at a low thermal budget process. Based on experiment demonstrations over the past 10 years, it is well known that HZO films show excellent ferroelectricity when sandwiched between TiN top and bottom electrodes. This work reports a comprehensive study on the effect of TiN top and bottom electrodes on the ferroelectric properties of HZO thin films (10 nm). Investigations showed that during HZO crystallization, the TiN bottom electrode promoted ferroelectric phase formation (by oxygen scavenging) and the TiN top electrode inhibited non-ferroelectric phase formation (by stress-induced crystallization). In addition, it was confirmed that the TiN top and bottom electrodes acted as a barrier layer to hydrogen diffusion into the HZO thin film during annealing in a hydrogen-containing atmosphere. These features make the TiN electrodes a useful strategy for improving and preserving the ferroelectric properties of HZO thin films for next-generation memory applications.

Low-Thermal-Budget Doping of 2D Materials in Ambient Air Exemplified by Synthesis of Boron-Doped Reduced Graphene Oxide.

Graphene oxide (GO) doping and reduction allow for physicochemical property modification to suit practical application needs. Herein, the challenge of simultaneous low-thermal-budget heteroatom doping of GO and its reduction in ambient air is addressed through the synthesis of B-doped reduced GO (B@rGO) by flash irradiation of boric acid loaded onto a GO support with intense pulsed light (IPL). The effects of light power and number of shots on the in-depth sequential doping and reduction mechanisms are investigated by ex situ X-ray photoelectron spectroscopy and direct millisecond-scale temperature measurements (temperature >1600 °C, < 10-millisecond duration, ramping rate of 5.3 × 105 °C s-1). Single-flash IPL allows the large-scale synthesis of substantially doped B@rGO (≈3.60 at% B) to be realized with a thermal budget 106-fold lower than that of conventional thermal methods, and the prepared material with abundant B active sites is employed for highly sensitive and selective room-temperature NO2 sensing. Thus, this work showcases the great potential of optical annealing for millisecond-scale ultrafast reduction and heteroatom doping of GO in ambient air, which allows the tuning of multiple physicochemical GO properties.

Hard-Baked Photoresist as a Sacrificial Layer for Sub-180 °C Surface Micromachining Processes.

This letter proposes a method for utilizing a positive photoresist, Shipley 1805, as a sacrificial layer for sub-180 °C fabrication process flows. In the proposed process, the sacrificial layer is etched at the end to release the structures using a relatively fast wet-etching technique employing resist remover and a critical point dryer (CPD). This technique allows high etching selectivity over a large number of materials, including silicon-based structural materials such as silicon-carbide, metals such as titanium and aluminum, and cured polymers. This selectivity, as well as the low processing thermal budget, introduces more flexibility in material selection for monolithic integration above complementary metal oxide semiconductor (CMOS) as well as flexible substrates.

Can mantle convection be self-regulated?

The notion of self-regulating mantle convection, in which heat loss from the surface is constantly adjusted to follow internal radiogenic heat production, has been popular for the past six decades since Urey first advocated the idea. Thanks to its intuitive appeal, this notion has pervaded the solid earth sciences in various forms, but approach to a self-regulating state critically depends on the relation between the thermal adjustment rate and mantle temperature. I show that, if the effect of mantle melting on viscosity is taken into account, the adjustment rate cannot be sufficiently high to achieve self-regulation, regardless of the style of mantle convection. The evolution of terrestrial planets is thus likely to be far from thermal equilibrium and be sensitive to the peculiarities of their formation histories. Chance factors in planetary formation are suggested to become more important for the evolution of planets that are more massive than Earth.

Effects of temperature elevation on a field population of Acyrthosiphon svalbardicum (Hemiptera: Aphididae) on Spitsbergen.

A manipulation experiment was carried out on a field population of the aphid Acyrthosiphon svalbardicum near Ny Ålesund, on the high arctic island of Spitsbergen, using cloches to raise temperature. An average rise in temperature of 2.8 deg. C over the summer season markedly advanced the phenology of both the host plant Dryas octopetala and the aphid. Advanced aphid phenology, with concomitant increases in reproductive output and survival, and successful completion of the life-cycle led to an eleven-fold increase in the number of overwintering eggs. Thermal budget requirements in day degrees above 0°C were calculated for key life-cycle stages of the aphid. Temperature data from Ny Ålesund over the past 23 years were used to calculate thermal budgets for the field site over the same period and these were compared with the requirements of the aphid. Each estimated thermal budget was then adjusted to simulate the effect of a +2, +4, and -2deg. C change in average temperature on aphid performance. This retrospective analysis (i) confirms that the life-cycle of A. svalbardicum is well suited to exploit higher summer temperatures, (ii) indicates that the annual success of local populations are sensitive to small changes in temperature and (iii) suggests that the aphid is living at the limits of its thermal range at Ny Ålesund based on its summer thermal budget requirements.