The future transistors.

The metal-oxide-semiconductor field-effect transistor (MOSFET), a core element of complementary metal-oxide-semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

Parametric Amplifiers Based on Quantum Dots.

Josephson parametric amplifiers (JPAs) approaching quantum-limited noise performance have been instrumental in enabling high fidelity readout of superconducting qubits and, recently, semiconductor quantum dots (QDs). We propose that the quantum capacitance arising in electronic two-level systems (the dual of Josephson inductance) can provide an alternative dissipationless nonlinear element for parametric amplification. We experimentally demonstrate phase-sensitive parametric amplification using a QD-reservoir electron transition in a CMOS nanowire split-gate transistor embedded in a 1.8 GHz superconducting lumped-element microwave cavity, achieving parametric gains of -3 to +3 dB, limited by Sisyphus dissipation. Using a semiclassical model, we find an optimized design within current technological capabilities could achieve gains and bandwidths comparable to JPAs, while providing complementary specifications with respect to integration in semiconductor platforms or operation at higher magnetic fields.

Remote Capacitive Sensing in Two-Dimensional Quantum-Dot Arrays.

We investigate gate-induced quantum dots in silicon nanowire field-effect transistors fabricated using a foundry-compatible fully depleted silicon-on-insulator (FD-SOI) process. A series of split gates wrapped over the silicon nanowire naturally produces a 2 × n bilinear array of quantum dots along a single nanowire. We begin by studying the capacitive coupling of quantum dots within such a 2 × 2 array and then show how such couplings can be extended across two parallel silicon nanowires coupled together by shared, electrically isolated, "floating" electrodes. With one quantum dot operating as a single-electron-box sensor, the floating gate serves to enhance the charge sensitivity range, enabling it to detect charge state transitions in a separate silicon nanowire. By comparing measurements from multiple devices, we illustrate the impact of the floating gate by quantifying both the charge sensitivity decay as a function of dot-sensor separation and configuration within the dual-nanowire structure.

Single-Electron Operation of a Silicon-CMOS 2 × 2 Quantum Dot Array with Integrated Charge Sensing.

The advanced nanoscale integration available in CMOS technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot formation and spin blockade in CMOS foundry-compatible devices are encouraging, but results are yet to match the control of individual electrons demonstrated in university-fabricated multigate designs. We show that quantum dots formed in a CMOS nanowire device can be measured with a remote single electron transistor (SET) formed in an adjacent nanowire, via floating coupling gates. By biasing the SET nanowire with respect to the nanowire hosting the quantum dots, we controllably form ancillary quantum dots under the floating gates, thus enabling control of all quantum dots in a 2 × 2 array, and charge sensing down to the last electron in each dot. We use effective mass theory to investigate the ideal geometrical parameters in order to achieve interdot tunnel rates required for spin-based quantum computation.

Electrical Spin Driving by g-Matrix Modulation in Spin-Orbit Qubits.

In a semiconductor spin qubit with sizable spin-orbit coupling, coherent spin rotations can be driven by a resonant gate-voltage modulation. Recently, we have exploited this opportunity in the experimental demonstration of a hole spin qubit in a silicon device. Here we investigate the underlying physical mechanisms by measuring the full angular dependence of the Rabi frequency, as well as the gate-voltage dependence and anisotropy of the hole g factor. We show that a g-matrix formalism can simultaneously capture and discriminate the contributions of two mechanisms so far independently discussed in the literature: one associated with the modulation of the g factor, and measurable by Zeeman energy spectroscopy, the other not. Our approach has a general validity and can be applied to the analysis of other types of spin-orbit qubits.

Level Spectrum and Charge Relaxation in a Silicon Double Quantum Dot Probed by Dual-Gate Reflectometry.

We report on dual-gate reflectometry in a metal-oxide-semiconductor double-gate silicon transistor operating at low temperature as a double quantum dot device. The reflectometry setup consists of two radio frequency resonators respectively connected to the two gate electrodes. By simultaneously measuring their dispersive responses, we obtain the complete charge stability diagram of the device. Electron transitions between the two quantum dots and between each quantum dot and either the source or the drain contact are detected through phase shifts in the reflected radio frequency signals. At finite bias, reflectometry allows probing charge transitions to excited quantum-dot states, thereby enabling direct access to the energy level spectra of the quantum dots. Interestingly, we find that in the presence of electron transport across the two dots the reflectometry signatures of interdot transitions display a dip-peak structure containing quantitative information on the charge relaxation rates in the double quantum dot.

Few-electron edge-state quantum dots in a silicon nanowire field-effect transistor.

We investigate the gate-induced onset of few-electron regime through the undoped channel of a silicon nanowire field-effect transistor. By combining low-temperature transport measurements and self-consistent calculations, we reveal the formation of one-dimensional conduction modes localized at the two upper edges of the channel. Charge traps in the gate dielectric cause electron localization along these edge modes, creating elongated quantum dots with characteristic lengths of ∼10 nm. We observe single-electron tunneling across two such dots in parallel, specifically one in each channel edge. We identify the filling of these quantum dots with the first few electrons, measuring addition energies of a few tens of millielectron volts and level spacings of the order of 1 meV, which we ascribe to the valley orbit splitting. The total removal of valley degeneracy leaves only a 2-fold spin degeneracy, making edge quantum dots potentially promising candidates for silicon spin qubits.

Strong coupling between a photon and a hole spin in silicon.

Spins in semiconductor quantum dots constitute a promising platform for scalable quantum information processing. Coupling them strongly to the photonic modes of superconducting microwave resonators would enable fast non-demolition readout and long-range, on-chip connectivity, well beyond nearest-neighbour quantum interactions. Here we demonstrate strong coupling between a microwave photon in a superconducting resonator and a hole spin in a silicon-based double quantum dot issued from a foundry-compatible metal-oxide-semiconductor fabrication process. By leveraging the strong spin-orbit interaction intrinsically present in the valence band of silicon, we achieve a spin-photon coupling rate as high as 330 MHz, largely exceeding the combined spin-photon decoherence rate. This result, together with the recently demonstrated long coherence of hole spins in silicon, opens a new realistic pathway to the development of circuit quantum electrodynamics with spins in semiconductor quantum dots.

Few electron limit of n-type metal oxide semiconductor single electron transistors.

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.

Single-electron operations in a foundry-fabricated array of quantum dots.

Silicon quantum dots are attractive for the implementation of large spin-based quantum processors in part due to prospects of industrial foundry fabrication. However, the large effective mass associated with electrons in silicon traditionally limits single-electron operations to devices fabricated in customized academic clean rooms. Here, we demonstrate single-electron occupations in all four quantum dots of a 2 x 2 split-gate silicon device fabricated entirely by 300-mm-wafer foundry processes. By applying gate-voltage pulses while performing high-frequency reflectometry off one gate electrode, we perform single-electron operations within the array that demonstrate single-shot detection of electron tunneling and an overall adjustability of tunneling times by a global top gate electrode. Lastly, we use the two-dimensional aspect of the quantum dot array to exchange two electrons by spatial permutation, which may find applications in permutation-based quantum algorithms.

Gate-based high fidelity spin readout in a CMOS device.

The engineering of a compact qubit unit cell that embeds all quantum functionalities is mandatory for large-scale integration. In addition, these functionalities should present the lowest error rate possible to successfully implement quantum error correction protocols1. Electron spins in silicon quantum dots are particularly promising because of their high control fidelity2-5 and their potential compatibility with complementary metal-oxide-semiconductor industrial platforms6,7. However, an efficient and scalable spin readout scheme is still missing. Here we demonstrate a high fidelity and robust spin readout based on gate reflectometry in a complementary metal-oxide-semiconductor device that consists of a qubit dot and an ancillary dot coupled to an electron reservoir. This scalable method allows us to read out a spin in a single-shot manner with an average fidelity above 98% for a 0.5 ms integration time. To achieve such a fidelity, we combine radio-frequency gate reflectometry with a latched spin blockade mechanism that requires electron exchange between the ancillary dot and the reservoir. We show that the demonstrated high readout fidelity is fully preserved up to 0.5 K. This result holds particular relevance for the future cointegration of spin qubits and classical control electronics.