Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels.

In this study, we investigate the gate-bias stability of triple-gated feedback field-effect transistors (FBFETs) with Si nanosheet channels. The subthreshold swing (SS) of FBFETs increases from 0.3 mV dec-1to 60 and 80 mV dec-1inp- andn-channel modes, respectively, when a positive bias stress (PBS) is applied for 1000 s. In contrast, the SS value does not change even after a negative bias stress (NBS) is applied for 1000 s. The difference in the switching characteristics under PBS and NBS is attributed to the ability of the interface traps to readily gain electrons from the inversion layer. The switching characteristics deteriorated by PBS are completely recovered after annealing at 300 °C for 10 min, and the characteristics remain stable even after PBS is applied again for 1000 s.

One-Step Passivation of Both Sulfur Vacancies and SiO2 Interface Traps of MoS2 Device.

Transition metal dichalcogenides (TMDs) benefit electrical devices with spin-orbit coupling and valley- and topology-related properties. However, TMD-based devices suffer from traps arising from defect sites inside the channel and the gate oxide interface. Deactivating them requires independent treatments, because the origins are dissimilar. This study introduces a single treatment to passivate defects in a multilayer MoS2 FET. By applying back-gate bias, protons from an H-TFSI droplet are injected into the MoS2, penetrating deeply enough to reach the SiO2 gate oxide. The characterizations employing low-temperature transport and deep-level transient spectroscopy (DLTS) studies reveal that the trap density of S vacancies in MoS2 drops to the lowest detection level. The temperature-dependent mobility plot on the SiO2 substrate resembles that of the h-BN substrate, implying that dangling bonds in SiO2 are passivated. The carrier mobility on the SiO2 substrate is enhanced by approximately 2200% after the injection.

Interface engineering of 9X stacked 3D NAND flash memory using hydrogen post-treatment annealing.

This study investigates the effects of hydrogen post-treatment on 3D NAND flash memory. Hydrogen post-treatment annealing (PTA) is suggested to passivate the defects in the tunneling oxide/poly-Si interface and inside the poly-Si channel. However, excess hydrogen PTA can release hydrogen atoms from the passivated defects, which may degrade device performance. Therefore, it is important to determine the appropriate PTA condition for optimization of the device performance. Three different conditions for hydrogen PTA, namely Reference, H, and H++, are applied to observe the effects on device performance. The activation energy (Ea) of the device parameters was extracted according to the hydrogen PTA condition to analyze the effects. The extractedEais about 74 meV for Reference, 53 meV for H, and 58 meV for H++conditions, with the best performance observed at the H condition. Optimal hydrogen PTA shows the best on-current (51% higher than Reference) and stable short-term retention (66% suppressedΔVTthan Reference) in 9X stacked 3D NAND flash memory.

Temperature Dependence According to Grain Boundary Potential Barrier Variation in Vertical NAND Flash Cell with Polycrystalline-Silicon Channel.

We investigate the electrical characteristics according to changing temperature on trap distribution in the energy gap of grain boundary (GB) and interface trap density (D(it)) between polycrystalline-silicon (poly-Si) channel and tunnel oxide in Vertical NAND (VNAND) flash cell with poly-Si channel. We confirmed that there are two factors changing GB potential barrier height such as trap distribution in GB and D(it) using technology computer-aided design (TCAD) simulation. Also, we found that the electrical characteristics according to changing temperature are significantly dependent on height and position of GB potential barrier in VNAND flash cell with poly-Si channel. We expect that it is required to develop more accurate extraction method for trap distribution in each GB and D(it) for better understanding temperature dependence of electrical characteristics in VNAND Flash cell.

Alloyed 2D Metal-Semiconductor Heterojunctions: Origin of Interface States Reduction and Schottky Barrier Lowering.

The long-term stability and superior device reliability through the use of delicately designed metal contacts with two-dimensional (2D) atomic-scale semiconductors are considered one of the critical issues related to practical 2D-based electronic components. Here, we investigate the origin of the improved contact properties of alloyed 2D metal-semiconductor heterojunctions. 2D WSe2-based transistors with mixed transition layers containing van der Waals (M-vdW, NbSe2/WxNb1-xSe2/WSe2) junctions realize atomically sharp interfaces, exhibiting long hot-carrier lifetimes of approximately 75,296 s (78 times longer than that of metal-semiconductor, Pd/WSe2 junctions). Such dramatic lifetime enhancement in M-vdW-junctioned devices is attributed to the synergistic effects arising from the significant reduction in the number of defects and the Schottky barrier lowering at the interface. Formation of a controllable mixed-composition alloyed layer on the 2D active channel would be a breakthrough approach to maximize the electrical reliability of 2D nanomaterial-based electronic applications.

Electron Excess Doping and Effective Schottky Barrier Reduction on the MoS2/h-BN Heterostructure.

Layered hexagonal boron nitride (h-BN) thin film is a dielectric that surpasses carrier mobility by reducing charge scattering with silicon oxide in diverse electronics formed with graphene and transition metal dichalcogenides. However, the h-BN effect on electron doping concentration and Schottky barrier is little known. Here, we report that use of h-BN thin film as a substrate for monolayer MoS2 can induce ∼6.5 × 1011 cm-2 electron doping at room temperature which was determined using theoretical flat band model and interface trap density. The saturated excess electron concentration of MoS2 on h-BN was found to be ∼5 × 1013 cm-2 at high temperature and was significantly reduced at low temperature. Further, the inserted h-BN enables us to reduce the Coulombic charge scattering in MoS2/h-BN and lower the effective Schottky barrier height by a factor of 3, which gives rise to four times enhanced the field-effect carrier mobility and an emergence of metal-insulator transition at a much lower charge density of ∼1.0 × 1012 cm-2 (T = 25 K). The reduced effective Schottky barrier height in MoS2/h-BN is attributed to the decreased effective work function of MoS2 arisen from h-BN induced n-doping and the reduced effective metal work function due to dipole moments originated from fixed charges in SiO2.

Study on the Hydrogen Effect and Interface/Border Traps of a Depletion-Mode AlGaN/GaN High-Electron-Mobility Transistor with a SiNx Gate Dielectric at Different Temperatures.

In this study, the electrical characteristics of depletion-mode AlGaN/GaN high-electron-mobility transistors (HEMTs) with a SiNx gate dielectric were tested under hydrogen exposure conditions. The experimental results are as follows: (1) After hydrogen treatment at room temperature, the threshold voltage VTH of the original device was positively shifted from -16.98 V to -11.53 V, and the positive bias of threshold was 5.45 V. When the VDS was swept from 0 to 1 V with VGS of 0 V, the IDS was reduced by 25% from 9.45 A to 7.08 A. (2) Another group of original devices with identical electrical performance, after the same duration of hydrogen treatment at 100 °C, exhibited a reverse shift in threshold voltage with a negative threshold shift of -0.91 V. The output characteristics were enhanced, and the saturation leakage current was increased. (3) The C-V method and the low-frequency noise method were used to investigate the effect of hydrogen effect on the device interface trap and border trap, respectively. It was found that high-temperature hydrogen conditions can passivate the interface/border traps of SiNx/AlGaN, reducing the density of interface/border traps and mitigating the trap capture effect. However, in the room-temperature hydrogen experiment, the concentration of interface/border traps increased. The research findings in this paper provide valuable references for the design and application of depletion-mode AlGaN/GaN HEMT devices.

Effect of interface defects on electrical characteristics of a-ITGZO TFTs under bottom, top, and dual gatings.

Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm2/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.6 cm2/V∙s, 301 mV/decade) and bottom (11.1 cm2/V∙s, 487 mV/decade) gatings. For an a-ITGZO TFT, oxygen deficiencies are more prevalent in the bottom-gate dielectric interface than in the top-gate dielectric interface, and they are less prevalent inside the channel layer than at the interfaces, indicating that the presence of oxygen deficiencies significantly affects the field-effect mobility and subthreshold swing. Moreover, the variation in the electrical characteristics due to the positive bias stress is discussed here.

H2 Plasma and PMA Effects on PEALD-Al2O3 Films with Different O2 Plasma Exposure Times for CIS Passivation Layers.

In this study, the electrical properties of Al2O3 film were analyzed and optimized to improve the properties of the passivation layer of CMOS image sensors (CISs). During Al2O3 deposition processing, the O2 plasma exposure time was adjusted, and H2 plasma treatment as well as post-metallization annealing (PMA) were performed as posttreatments. The flat-band voltage (Vfb) was significantly shifted (ΔVfb = 2.54 V) in the case of the Al2O3 film with a shorter O2 plasma exposure time; however, with a longer O2 plasma exposure time, Vfb was slightly shifted (ΔVfb = 0.61 V) owing to the reduction in the carbon impurity content. Additionally, the as-deposited Al2O3 sample with a shorter O2 plasma exposure time had a larger number of interface traps (interface trap density, Dit = 8.98 × 1013 eV-1·cm-2). However, Dit was reduced to 1.12 × 1012 eV-1·cm-2 by increasing the O2 plasma exposure time and further reduced after PMA. Consequently, we fabricated an Al2O3 film suitable for application as a CIS passivation layer with a reduced number of interface traps. However, the Al2O3 film with increased O2 plasma exposure time deteriorated owing to plasma damage after H2 plasma treatment, which is a method of reducing carbon impurity content. This deterioration was validated using the C-V hump and breakdown characteristics.

Investigation of Anomalous Degradation Tendency of Low-Frequency Noise in Irradiated SOI-NMOSFETs.

In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at different irradiation doses and separate the threshold-voltage shifts caused by the oxide-trap charge and interface-trap charge. Moreover, the increased densities of the oxide-trap charge projected to the Si/SiO2 interface and interface-trap charge are calculated. The results of our experiment suggest that the magnitudes of low-frequency noise do not necessarily increase with the increase in border-trap density. A novel physical explanation for the low-frequency noise in SOI-NMOSFETs with high interface-trap density is proposed. We reveal that the presence of high-density interface traps after irradiation has a repressing effect on the generation of low-frequency noise. Furthermore, the exchange of some carriers between border traps and interface traps can cause a decrease in the magnitude of low-frequency noise when the interface-trap density is high.

Extraction of Interface-Trap Densities of the Stacked Bonding Structure in 3D Integration Using High-Frequency Capacitance-Voltage Technique.

An extraction method of the interface-trap densities (Dit) of the stacked bonding structure in 3D integration using high-frequency capacitance-voltage technique is proposed. First, an accurate high-frequency capacitance-voltage model is derived. Next, by numerically solving the charge-balance equation and charge conservation equation, Dit is extracted by fitting the measured and calculated capacitance-voltage curves based on the derived model. Subsequently, the accuracy of the derived model is verified by the agreements between the analytical results and TCAD simulation results. The average extraction error proves the precision and efficiency of the extraction method. Finally, the stacked bonding structure has been fabricated, and Dit at the interface between silicon and insulator is extracted to diagnose and calibrate the fabrication processes.

Interface Trap Suppression and Electron Doping in Van der Waals Materials Using Cross-Linked Poly(vinylpyrrolidone).

The instability of van der Waals (vdW) materials leads to spontaneous morphological and chemical transformations in the air. Although the passivation of vdW materials with other resistive materials is often used to solve stability issues, this passivation layer can block carrier injection and thus interfere with charge transfer doping. In this study, a facile method is proposed for n-doping and mediation of Se vacancies in tungsten diselenide (WSe2) by poly(vinylpyrrolidone) (PVP) coating. The major carrier type of the PVP-coated WSe2-based field-effect transistor (FET) was converted from hole (p-type) to electron (n-type). Furthermore, the vacancy-induced interface trap density was reduced by approximately 500 times. This study provides a practical doping and passivation method for the van der Waals materials, as well as a comprehensive understanding of the chemical reaction and electronic transport in these materials.

Interface Trap-Induced Temperature Dependent Hysteresis and Mobility in ß-Ga2O3 Field-Effect Transistors.

Interface traps between a gate insulator and beta-gallium oxide (ß-Ga2O3) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20-300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges' trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases.

Performance Enhancement in N2 Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlOX Gate Dielectric with Γ-Shaped Gate Engineering.

In this paper, we have demonstrated the optimized device performance in the Γ-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO2 and comparing it with the commonly used HfO2 gate dielectric with the N2 surface plasma treatment. The inclusion of Al in the HfO2 increased the crystalline temperature (~1000 °C) of hafnium aluminate (HfAlOX) and kept the material in the amorphous stage even at very high annealing temperature (>800 °C), which subsequently improved the device performance. The gate leakage current (IG) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 °C in HfAlOX-based MOS-HEMT, compared to the HfO2-based device. In comparison with HfO2 gate dielectric, the interface state density (Dit) can be reduced significantly using HfAlOX due to the effective passivation of the dangling bond. The greater band offset of the HfAlOX than HfO2 reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower IG in Γ-gate HfAlOX MOS-HEMT. Moreover, IG was reduced more than one order of magnitude in HfAlOX MOS-HEMT by the N2 surface plasma treatment, due to reduction of N2 vacancies which were created by ICP dry etching. The N2 plasma treated Γ-shaped gate HfAlOX-based MOS-HEMT exhibited a decent performance with IDMAX of 870 mA/mm, GMMAX of 118 mS/mm, threshold voltage (VTH) of -3.55 V, higher ION/IOFF ratio of approximately 1.8 × 109, subthreshold slope (SS) of 90 mV/dec, and a high VBR of 195 V with reduced gate leakage current of 1.3 × 10-10 A/mm.

Characterization of Electrical Traps Formed in Al2O3 under Various ALD Conditions.

Frequency dispersion in the accumulation region seen in multifrequency capacitance-voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al2O3 dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps-i.e., interface traps-are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.

Border Trap Characterizations of Al2O3/ZrO2 and Al2O3/HfO2 Bilayer Films Based on Ambient Post Metal Annealing and Constant Voltage Stress.

This study represents a comparison of the border trap behavior and reliability between HfO2 and ZrO2 films on n-In0.53Ga0.47As with an Al2O3 interfacial layer. The effect of different post metal annealing conditions on the trap response was analyzed and it was found that the N2:H2 mixed FGA passivates the border trap quite well, whereas N2-based RTA performs better on interface traps. Al2O3/HfO2 showed more degradation in terms of the threshold voltage shift while Al2O3/ZrO2 showed higher leakage current behavior. Moreover, Al2O3/ZrO2 showed a higher permittivity, hysteresis, and breakdown field than Al2O3/HfO2.

Characterization of Al Incorporation into HfO2 Dielectric by Atomic Layer Deposition.

This study presents the characteristics of HfAlO films for a series of Al incorporation ratios into a HfO2 dielectric by atomic layer deposition on a Si substrate. A small amount of Al doping into the HfO2 film can stabilize the tetragonal phase of the HfO2, which helps to achieve a higher dielectric constant (k) and lower leakage current density, as well as a higher breakdown voltage than HfO2 film on its own. Moreover, assimilation of Al2O3 into HfO2 can reduce the hysteresis width and frequency dispersion. These are indications of border trap reduction, which was also verified by the border trap extraction mechanism. X-ray photoelectron spectroscopy (XPS) analysis also verified the HfAlO microstructural properties for various Al compositions. In addition, higher amounts of Al2O3 in HfAlO resulted in better interface and dielectric behavior through trap minimization, although the equivalent-oxide-thickness (EOT) values show the opposite trend.

Influence of Oxygen-Plasma Treatment on In-Situ SiN/AlGaN/GaN MOSHEMT with PECVD SiO2 Gate Insulator.

The influence of oxygen-plasma treatment on in situ SiN/AlGaN/GaN MOS high electron mobility transistor with SiO2 gate insulator was investigated. Oxygen-plasma treatment was performed on in situ SiN, before SiO2 gate insulator was deposited by plasma-enhanced chemical vapor deposition (PECVD). DC I-V characteristics were not changed by oxygen plasma treatment. However, pulsed I-V characteristics were improved, showing less dispersion compared to non-treated devices. During short-term gate bias stress, the threshold voltage shift was also smaller in a treated device than in an untreated one. X-ray photoemission spectroscopy also revealed that SiO2 on in situ SiN with oxygen-plasma treatment has an O/Si ratio close to the theoretical value. This suggests that the oxygen plasma treatment-modified surface condition of the SiN layer is favorable to SiO2 formation by PECVD.

Negative Fermi-Level Pinning Effect of Metal/n-GaAs(001) Junction Induced by a Graphene Interlayer.

It is demonstrated that the electric dipole layer due to the overlapping of electron wave functions at the metal/graphene contact results in a negative Fermi-level pinning effect on the region of the GaAs surface with low interface-trap density in the metal/graphene/n-GaAs(001) junction. The graphene interlayer plays the role of a diffusion barrier, preventing the atomic intermixing at the interface and preserving the low interface-trap density region. The negative Fermi-level pinning effect is supported by the decrease of the Schottky barrier with the increase of the metal work function. Our work shows that the graphene interlayer can invert the effective work function of the metal between high and low, making it possible to form both Schottky and Ohmic-like contacts with identical (particularly high work function) metal electrodes on a semiconductor substrate possessing low surface-state density.

Engineering High- k/SiGe Interface with ALD Oxide for Selective GeO x Reduction.

Suppression of electronic defects induced by GeO x at the high- k gate oxide/SiGe interface is critical for implementation of high-mobility SiGe channels in complementary metal-oxide-semiconductor (CMOS) technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO x-rich interlayer on SiGe. Experimental studies in the literature indicate a better interface formation with Al2O3 in contrast to HfO2 on SiGe; however, the mechanism behind this is not well understood. In this study, the mechanism of forming a low defect density interface between Al2O3/SiGe is investigated using atomic layer deposited (ALD) Al2O3 insertion into or on top of ALD HfO2 gate oxides. To elucidate the mechanism, correlations are made between the defect density determined by impedance measurements and the chemical and physical structures of the interface determined by high-resolution scanning transmission electron microscopy and electron energy loss spectroscopy. The compositional analysis reveals an SiO x rich interlayer for both Al2O3/SiGe and HfO2/SiGe interfaces with the insertion of Al2O3 into or on top of the HfO2 oxide. The data is consistent with the Al2O3 insertion inducing decomposition of the GeO x from the interface to form an electrically passive, SiO x rich interface on SiGe. This mechanism shows that nanolaminate gate oxide chemistry cannot be interpreted as resulting from a simple layer-by-layer ideal ALD process, because the precursor or its reaction products can diffuse through the oxide during growth and react at the semiconductor interface. This result shows that in scaled CMOS, remote oxide ALD (oxide ALD on top of the gate oxide) can be used to suppress electronic defects at gate oxide semiconductor interfaces by oxygen scavenging.