Effects of a 12-week home-based exercise program on quality of life, psychological health, and the level of physical activity in colorectal cancer survivors: a randomized controlled trial.

PURPOSE: To examine the effects of a home-based exercise program on quality of life (QOL), psychological health, and the level of physical activity (PA) in colorectal cancer survivors. METHODS: Seventy-one colorectal cancer survivors were randomized into either a home-based exercise group (N = 37) or control group (N = 34). The home-based exercise program included unsupervised walking, stationary bike, or swimming for aerobic exercise, as well as resistance exercise DVDs, a pedometer, and an exercise log. The Functional Assessment of Cancer Therapy-Colorectal, Functional Assessment of Chronic Illness Therapy-Fatigue Scale, patient health questionnaire, and Godin Leisure-Time Exercise Questionnaire were used to assess QOL, fatigue, depression, and PA levels. RESULTS: Among the 71 participants, 30 in the exercise group and 28 in the control group completed the study. The change in the QOL between the intervention and control groups was insignificant. However, QOL was significantly improved in the exercise group (QOL, p = 0.024). Sub-domain of QOL, emotional well-being, and trial outcome index-physical/functional/colorectal (p = 0.015 and p = 0.035, respectively) were improved in the exercise group. The level of PA was significantly increased after 12 weeks in the exercise group (97.0 ± 188.5 vs. 332.6 ± 306.1, p < 0.001), and the change significantly differed compared with the control group (mean change 235.6 vs. 16.3, p < 0.001). CONCLUSIONS: The home-based exercise program may improve the QOL and psychological health in colorectal cancer survivors. We have demonstrated that the home-based exercise program was effective in increasing the level of PA in colorectal cancer survivors.

Capacitorless One-Transistor Dynamic Random-Access Memory Based on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time.

We present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a Si/SiGe heterojunction double-gate MOSFET. In the proposed 1T-DRAM, the program process is based on band-to-band tunneling (BTBT) between gate 1 and gate 2 regions, and a sensing margin is defined by the amount of excess holes stored in the SiGe body region. Therefore, the sensing margin and retention time were affected by SiGe in the body region. The BTBT rate, enhanced by the small band-gap energy in SiGe, increased the sensing margin. The Si/SiGe heterojunction between the source/drain and body regions formed a potential barrier for hole carriers. The retention time was improved by suppressing the diffusion of hole carriers in the floating-body storage node. In addition, the retention characteristic was also enhanced by applying a gate underlap structure, which significantly reduced the electric field-induced recombination rate. The optimized device with a Si0.7Ge0.3 body and underlap length (Lunderlap) of 5 nm exhibited a high sensing margin of 6.16 µA/µm and long retention time of 131 ms at a high temperature of 358 K.

Design Optimization of InGaAs/GaAsSb-Based P-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor.

In this work, an InGaAs/GaAsSb-based P-type gate-all-around (GAA) arch-shaped tunneling fieldeffect transistor (TFET) was designed and analyzed using technology computer-aided design (TCAD) simulations. The device performance was investigated in views of the on-state current (Ion), subthreshold swing (SS), and Ion/Ioff ratio. For high current drivability, InGaAs/GaAsSb heterojunction is used to form the broken bandgap. Owing to the GAA arch-shaped structure of the TFET, the tunneling region between source and channel extended, thus Ion and SS are improved. However, it has some performance variations that are related with the height of the source region (Hsource), the epitaxially grown thickness of the channel (tepi), and the height of the drain region (Hdrain). Therefore, we performed a design optimization of the proposed device with the variables of Hsource, tepi, and Hdrain. The designed and optimized InGaAs/GaAsSb-based P-type GAA arch-shaped TFET demonstrated an Ion of 215 µA/µm SS of 18 mV/dec and Ion/Ioff of 1.64 × 1012.

Analysis of Electrical Characteristics of InAlGaN/GaN-Based High Electron Mobility Transistors with AlGaN Back Barriers.

In this study, the effect of an AlGaN back-barrier on the electrical characteristics of InAlGaN/GaN high electron mobility transistors (HEMTs) was investigated. The dependence of the thickness and the Al composition of the AlGaN back-barrier on the off-state current (Ioff) of the devices was investigated. An InAlGaN/GaN HEMT with an Al0.1GaN back-barrier of thickness 20 nm exhibited lower Ioff because of the carrier confinement effect, which was caused by the back-barrier. The carrier confinement effect also improved the maximum output current density and the transconductance (gm). Thus, the obtained cut-off frequency (fT) and maximum oscillation frequency (fmax) values for the InAlGaN/GaN HEMT with the 20 nm thick AlGaN back-barrier were 2.6% and 13% higher than those without the AlGaN back-barrier. In addition, the impact of the buffer trap density and GaN channel thickness were evaluated. In the case of a thickness of 20 nm for the Al0.1GaN back-barrier, a low Ioff was maintained although the trap density in the buffer layer was changed. In addition, as the gate length (LGa) decreased to 50 nm, the InAlGaN/GaN HEMT with the 20 nm thick Al0.1GaN back-barrier achieved better Ioff characteristics, lower drain-induced barrier lowering (DIBL) of 85.8 mV/V, and subthreshold swing (S) of 269 mV/dec owing to a reduction in the short-channel effect.

Effect of Interface Traps on the Device Performance of InGaAs-Based Gate-All-Around Tunneling Field-Effect Transistors.

The effect of interface traps on InGaAs-based vertical gate-all-around (GAA) tunneling field-effect transistors (TFETs) has been investigated using technology computer-aided design (TCAD) simulation. The interface traps distributed within different energy levels (Et) in the energy bandgap of a semiconductor material exhibit various influences on the device performances. In this work, InGaAs-based TFETs are simulated to analyze the effects on the on-state current (Ion), off-state current (Ioff), threshold voltage (Vth), subthreshold swing (SS), and the ambipolar characteristics according to Et and type of the interface traps. We have confirmed that Ioff and SS are degraded by the interface traps. Further, it can be shown that Ion is mainly affected by the acceptor-like traps and ambipolar behavior is affected by the donor-like traps. All the effects increase as Et becomes closer to the midgap. The effects of the interface traps with gate underlap and overlap at the source-channel region also have been investigated, considering the device fabrication. Additionally, the analysis of the effect of junction trap created at the source-channel junction has been performed.

Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless FinFETs.

This paper report a junctionless fin-type field-effect-transistor based capacitorless dynamic random access memory using three-dimensional technology computer-aided design simulations. The proposed 1T-DRAM is made up of a silicon germanium storage region surrounding a silicon fin. When the two materials form a heterojunction, a potential well is formed by the band discontinuity which carriers can be stored. During the program operation, band-to-band tunneling and gate-induced drain leakage occur simultaneously due to the gate and drain bias. Because of these phenomena, the electron-hole pair occurs, and generated holes are stored in the storage region by potential well. The holes formed are positively charged within the storage region, which mitigates the depletion of the channel and improves the operating current. The proposed device realizes the memory operation by the difference of the operating current depending on the presence or absence of the stored holes. In this work, the device is analyzed and optimized in detail. The proposed 1T-DRAM shows excellent performance with a retention time of 161 ms based on 50% of the maximum data margin.

Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor.

In this study, one-transistor dynamic random-access memory (1T-DRAM) based on a symmetric double-gate Si junctionless transistor is proposed using technology computer-aided design simulation. The proposed device uses double gates that play different roles in realizing 1T-DRAM operation. Gate 1 is used as a switching node, and Gate 2 is used as a storage node. By controlling the different two gate workfunctions, a potential barrier is adjusted to store hole effectively. The operation characteristics were investigated regarding four different memory operation states to write "1", write "0", read, and hold. Also, the effects of two different gate workfunctions on sensing margin and retention characteristics are closely investigated. Through a set of optimally set gate workfunctions, 33 µA/µm of sensing margin and 38 ms of retention time have been obtained.

Empowering Tri-Functional Palladium's Catalytic Activity and Durability in Electrocatalytic Formic Acid Oxidation Reaction via Innovative Self-Caging and Alloying Strategies.

Direct formic acid fuel cells (DFAFCs) stand out for portable electronic devices owing to their ease of handling, abundant fuel availability, and high theoretical open circuit potential. However, the practical application of DFAFCs is hindered by the unsatisfactory performance of electrocatalysts for the sluggish anodic formic acid oxidation reaction (FAOR). Palladium (Pd) based nanomaterials have shown promise for FAOR due to their highly selective reaction mechanism, but maintaining high electrocatalytic durability remains challenging. In this study, a novel Pd-based electrocatalyst (UiO-Pd-E) is reported with exceptional durability and activity for FAOR, which can be attributed to the Pd nanoparticles encapsulated within a carbon framework where concurrent chemical alloying of Pd and Zr occurs. Further, the UiO-Pd-E demonstrates noteworthy multifunctionality in various electrochemical reactions including electrocatalytic ethanol oxidation reaction (EOR) and oxygen reduction reaction (ORR) in addition to the FAOR, highlighting its practical potentials.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 µA/µm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO2/Si3N4 Dual-Layer Insulator.

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO2/Si3N4 dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si3N4 single-layer insulator are conducted to the simulation works together. The stacked TiO2/Si3N4 GaN MOSFET has a maximum on-state current of 743.8 mA/mm, which is the improved value due to the larger oxide capacitance of TiO2/Si3N4 than that of a Si3N4 single-layer insulator. However, the electrical field and current density increased by the stacked TiO2/Si3N4 layers make the device's temperature higher. That results in the degradation of the device's performance. We simulated and analyzed the operation mechanisms of the GaN MOSFETs modulated by the SHEs in view of high-power and high-frequency characteristics. The maximum temperature inside the device was increased to 409.89 K by the SHEs. In this case, the stacked TiO2/Si3N4-based GaN MOSFETs had 25%-lower values for both the maximum on-state current and the maximum transconductance compared with the device where SHEs did not occur; Ron increased from 1.41 mΩ·cm2 to 2.56 mΩ·cm2, and the cut-off frequency was reduced by 26% from 5.45 GHz. Although the performance of the stacked TiO2/Si3N4-based GaN MOSFET is degraded by SHEs, it shows superior electrical performance than GaN MOSFETs with Si3N4 single-layer insulator.

Design of a Capacitorless Dynamic Random Access Memory Based on Junctionless Dual-Gate Field-Effect Transistor with a Silicon-Germanium/Silicon Nanotube.

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with a silicon-germanium (SiGe) and silicon (Si) nanotube structure was designed and investigated by using technology computer-aided design (TCAD) simulations. Utilizing bandgap engineering to make a quantum well in the core-shell structure, the storage pocket is formed by the difference in bandgap energy between SiGe and Si. By applying different voltage conditions at the inner gate and outer gate, excess holes are generated in the storage region by the band-to-band tunneling (BTBT) mechanism. The BTBT mechanism results in the floating body effect, which is the principle of 1T-DRAM. The varying amount of the accumulated holes in the SiGe region allows differentiating between state "1" and state "0." Additionally, the outer gate plays a role of the conventional gate, while the inner gate retains holes in the hold state by applying voltage. Consequently, the optimized SiGe/Si JLFET-based nanotube 1T-DRAM achieved a high sensing margin of 15.4 µA/µm, and a high retention time of 105 ms at a high temperature of 358 K. In addition, it has been verified that a single cycle of 1T-DRAM operations consumes only 33.6 fJ of energy, which is smaller than for previously proposed 1T-DRAMs.

The Effect of Grain Boundary on Electrical Characteristics in the Source and Drain Regions of Polycrystalline Silicon Based in One Transistor Dynamic Random Access Memory.

In this paper, we present a capacitorless one transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) double gate MOSFET with grain boundaries (GBs). Several studies have been conducted to implement 1T-DRAM using poly-Si. This is because poly-Si has the advantage of low-cost fabrication and can be stacked. However, poly-Si has GBs, which can adversely affect semiconductor device. So far, related studies on poly-Si-based 1T-DRAM have only focused on GBs present in the channel domain. Hence, in this study, we analyzed the transfer and memory characteristics when a GB is present in the source and drain regions. As a result, we found that in the center of the depletion region in the source and channel junction, where the effect of GB was most significant, sensing margins decreased the most from 0.88 to 0.29 µA/µm, and retention time (RT) decreased from 85 ms to 47 µs. In addition, we found that at the center of the depletion region in the drain and channel junction, where the effect of GBs was most significant in the drain region, RT decreased the most from 85 ms to 52 µs.

Design and Analysis of DC/DC Boost Converter Using Vertical GaN Power Device.

In this study, a high-performance vertical gallium nitride (GaN) power transistor is designed by using two-dimensional technology computer-aided design simulator. The vertical GaN transistor is used to analyze the DC/DC boost converter. The systems requiring high voltages of 1000 V or more, such as electric vehicles, need wide devices to achieve a high breakdown voltage when using conventional power devices. However, vertical GaN transistors can be fabricated with small device area and high breakdown voltage. The proposed device has an off-current of 4.72×10-10 A/cm², an on-current of 17,528 A/cm², and a high breakdown voltage of 1,265 V due to good gate controllability and the very long gate-to-drain length. Using the designed device, a boost converter that doubles the input voltage was constructed and is characteristics were examined. The designed boost converter obtained an output voltage of 1,951 V and the voltage conversion efficiency was considerably high at 97.55% when the input voltage was 1,000 V.

Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate.

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage), intrinsic region length (Lint), and operation bias conditions to obtain a high sensing margin of 49.7 µA/µm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS).

Recessed-Gate GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistor Using a Dual Gate-Insulator Employing TiO2/SiN.

In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO2/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO2/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO2 gate-insulator because of the high quality SiN gate-insulator. Therefore, the device using a dual gate-insulator can overcome disadvantages of a device using only TiO2 gate-insulator. To better predict the power consumption and the switching speed, we simulated the specific on-resistance (Ron, sp) according to the gate-to-drain distance (LGD) using the two-dimensional ATLAS simulator. The proposed device exhibits a threshold voltage of 2.3 V, a maximum drain current of 556 mA/mm, a low Ron, sp of 1.45 mΩ·cm², and a breakdown voltage of 631 V at an off-state current of 1 µA/mm with VGS = 0 V. We have confirmed that a normally-off recessed-gate AlGaN/GaN MIS-HEMT using a TiO2/SiN dual gate-insulator is a promising candidate for power electronic applications.

Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage.

In this work, a capacitorless one-transistor embedded dynamic random-access memory based on a metal-oxide-semiconductor field-effect transistor with a double-polysilicon layer structure has been proposed and investigated using technology computer-aided design simulation. By using the grain boundary for hole storage, a higher sensing margin of 4.35 /µA//µm is achieved compared to that without using the grain boundary. Furthermore, the proposed device achieves a superior retention time of 555.77 /µs, which is reasonable from the viewpoint of its application in embedded systems (>100 /µs), even at a high temperature of 358 K. For higher device reliability, the effect of the grain boundary on the capacitorless one-transistor embedded dynamic random-access memory is analyzed with different trap distributions. The proposed capacitorless one-transistor embedded dynamic random-access memory cell exhibited superior reliability in terms of retention time (>100 /µs).

Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary.

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.

Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances.

In this paper, we adopt the vertical core-shell nanowire field-effect transistors based on the Silicon-germanium (SiGe)/strained-silicon (strained-Si) layer as a method to improve the performance of the CMOS logic inverter by using technology computer aided design simulation. The lattice constant mismatch between the core region and the shell region causes the global strain of the Si region of the shell, which in turn changes the Si parameters. This phenomenon effects on the improvement the electrical characteristics in the p-type MOSFET (pMOSFET). Through this variation, the asymmetry of the electrical characteristics between n-type MOSFET (nMOSFET) and pMOSFET nanowire is considerably compensated. The inverter using the proposed core-shell structure shows the improved CMOS logic inverter characteristics. For example, the core-shell CMOS logic inverter shows performances such as NML = 0.315 V, NMH = 0.312 V, τPHL of 8.7 ps, and τPHL of 21 ps at an operating voltage of VDD = 0.7 V.

Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET.

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core-shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 µA/µm, off-state current (Ioff) of 1.09 × 10-12 A/µm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications.

Association Between Duration of Breast Feeding and Metabolic Syndrome: The Korean National Health and Nutrition Examination Surveys.

BACKGROUND: This study aimed to evaluate the association of the lifelong duration of breast feeding with metabolic syndrome (MetS) and its components in Korean parous women aged 19-50 years. MATERIALS AND METHODS: A total of 4724 participants from the Korean National Health and Nutritional Survey were included. Subjects were divided into four groups according to the duration of breast feeding: ≤5, 6-11, 12-23, or ≥24 months groups. The adjusted odds ratios (ORs) of MetS and its components were assessed according to the duration of breast feeding. RESULTS: Women who breastfed for 6-11 months had an OR of 0.67 (95% confidence interval [CI], 0.54-0.86) for elevated blood pressure (BP) compared with those who breastfed for ≤5 months after adjustment for possible confounders in a multivariable logistic regression analyses. Women who breastfed for 12-23 months were associated with an OR of 0.68 (95% CI, 0.54-0.86) for elevated BP, an OR of 0.78 (95% CI, 0.62-0.97) for elevated glucose, and an OR of 0.73 (95% CI, 0.56-0.95) for MetS compared with those who breastfed for ≤5 months in a multivariable logistic regression analyses. Women who breastfed for ≥24 months had an OR of 0.62 (95% CI, 0.52-0.84) for elevated glucose, an OR of 0.76 (95% CI, 0.60-0.96) for elevated triglycerides, and an OR of 0.70 (95% CI, 0.53-0.92) for MetS compared with those who breastfed for ≤5 months in a multivariable logistic regression analyses. CONCLUSIONS: Our results suggest that lifelong breast feeding for ≥12 months may be associated with lower risk for MetS.