Solution-processed zirconium acetylacetonate charge-trap layer for multi-bit nonvolatile thin-film memory transistors.

The charge trap property of solution-processed zirconium acetylacetonate (ZAA) for solution-processed nonvolatile charge-trap memory (CTM) transistors is demonstrated. Increasing the annealing temperature of the ZAA from room temperature (RT) to 300°C in ambient, the carbon double bonds within the ZAA decreases. The RT-dried ZAA for the p-type organic-based CTM shows the widest threshold voltage shift (∆VTH ≈ 80 V), four distinct VTHs for a multi-bit memory operation and retained memory currents for 103 s with high memory on- and off-current ratio (IM,ON/IM,OFF ≈ 5Ⅹ104). The n-type oxide-based CTM (Ox-CTM) also shows a ∆VTH of 14 V and retained memory currents for 103 s with IM,ON/IM,OFF ≈ 104. The inability of the Ox-CTM to be electrically erasable is well explained with simulated electrical potential contour maps. It is deduced that, irrespective of the varied solution-processed semiconductor used, the RT-dried organic ZAA as CTL shows the best memory functionality in the fabricated CTMs. This implies that the high carbon double bonds in the low-temperature processed ZAA CTL are very useful for low-cost multi-bit CTMs in flexible electronics.

Effect of Buffer Layer Capacitance on the Electrical Characteristics of Ferroelectric Polymer Capacitors and Field Effect Transistors.

We demonstrated the effect of a buffer layer on the electrical characteristics of ferroelectric polymer capacitors and field-effect transistors. Various polymer materials with a dielectric constant between 2 and 42 were used to form buffer layers with a similar thicknesses, but with different capacitances. In order to evaluate the characteristics of the ferroelectrics with a buffer layer, the polarization-voltage characteristics of the capacitor, the transfer characteristics, and the retention characteristics of the transistors were investigated. As the capacitance of the buffer layer increased, high remnant polarization (Pr), high hysteresis, and long retention times were observed. Exceptionally, when poly(methylmethacrylate) and rigid poly(aryl ether) (poly(9,9-bis(4-hydroxyphenyl)fluorene-co-decafluorobiphenyl)) were used as the buffer layer, Pr had a value close to 0 in the dynamic measurement polarization-voltage (P-V) characteristic, but the quasi-static measurement transfer characteristic and the static measurement retention characteristic showed relatively high hysteresis and long retention times. Our study provides a scientific and technical basis for the design of ferroelectric memory and neuromorphic devices.

Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure.

We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.

Solution-Processed Organic and Oxide Hybrid CMOS Inverter for Low Cost Electronic Circuits.

We demonstrated an organic and oxide hybrid CMOS inverter with the solution-processed semiconductor and source/drain electrodes. For the solution-processed n- and p-type semiconductor, InGaZnO solution and TIPS-pentacene/PαMS blend were spin-coated respectively while Silver ink and PEDOT:PSS solution were drop-casted with the help of the bank to serve as source/drain electrodes. The InGaZnO and the TIPS-pentacene transistors show typical n- and p-type transistor operations with low off-current. Based on the combination of the solution-processed n- and p-type transistors, full-swing characteristic curve with low static current of the hybrid CMOS were obtained.

Ferroelectric-Dielectric Mixed Buffer Layer for Enhanced Electrical Performance of Organic Ferroelectric Memory Transistors.

We suggest a facile method to reduce the surface roughness of the ferroelectric polymer insulator to enhance the electrical performance of the ferroelectric field effect memory transistors (FeFET). Ferroelectric-dielectric mixed buffer layer was used to reduce the high surface roughness of the single layer ferroelectric polymer insulator. The FeFET with mixed buffer bilayer (BL-FeFET) showed more than 25 times higher on-current (3.40 µA) compared with single layer FeFET (130 nA). The BL-FeFET showed enhanced memory retention, higher memory on-off ratio than the conventional single layer FeFET (SL-FeFET). The enhancement of the electrical performance of the BL-FeFET can be attributed to the smoothening of the rough needle-like grain surface morphology of the ferroelectric polymer insulator in the SL-FeFET. This process of mixed buffer polymer insulator may provide a technological method for production of high-performance nonvolatile FeFET memory devices.

Importance of Effective Surface Smoothness on the Electrical Performance of Organic Thin-Film Transistors.

We presented further analysis to explain how the surface morphology influence the mobility of the organic thin film transistors with gate insulator having large undulated surface (GU-OTFTs) and introduced a new parameter in order to clearly understand the relation between surface roughness and field-effect mobility. The average of the slope between two adjacent points on the surface of a gate insulator, or effective surface smoothness (ES), was closely investigated. A smooth-contact-pressing (SCP) process affected the surface smoothness of the P(VDF-TrFE) insulator with a significant change in root-mean-square roughness (Zrms). It was found that the ES gives better explanation for the variation of the field-effect mobility of the GU-OTFTs than the Zrms.